Simulation fails when it goes into big design.

Altera_Forum · ‎03-24-2010

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting..


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY deadband  IS
PORT (
        CLKOUT: IN STD_LOGIC;
        T3PWM: IN STD_LOGIC;
        PWMB7: OUT STD_LOGIC;
        PWMB8: OUT STD_LOGIC
        );
END deadband;
ARCHITECTURE identifier OF deadband IS
signal EVBCONDB_reg : UNSIGNED (7 downto 0) := "00011000";
signal PWMB7_DB_reg : STD_LOGIC;
signal PWMB8_DB_reg : STD_LOGIC;
BEGIN
  PWMB7 <= PWMB7_DB_reg;
  PWMB8 <= PWMB8_DB_reg;
-- T3PWM Deadband
-----------------
    process(CLKOUT,EVBCONDB_reg)
    variable prev_T3PWM    : STD_LOGIC;
    variable counter_en    : STD_LOGIC;
    variable count : UNSIGNED (8 downto 0);
    variable multiplier : UNSIGNED (2 downto 0);
    begin
    
        case EVBCONDB_reg(2 downto 0) is        
            when "110" => multiplier := "101"; -- /1 divisor
            when "111" => multiplier := "101";    -- /2 divisor
            when others => multiplier := EVBCONDB_reg(2 downto 0);    -- /32 default
        end case;
        if(rising_edge(CLKOUT)) then
-- if we see a transition, start the clock and enable deadband
            if(prev_T3PWM /= T3PWM) then
                counter_en := '1';
                --count := EVBCONDB_reg(6 downto 3) * multiplier;
                count := "00000" & EVBCONDB_reg(6 downto 3);
                count := count sll TO_INTEGER(multiplier);
            end if;
                
-- if we've reached 0, stop counting and disable deadband
            if(count = "000000000") then
                counter_en := '0';
-- else decrement counter by one
            else
                count := count - 1;
            end if;
-- remember T3PWM for next time
            prev_T3PWM := T3PWM;
-- and output delayed PWM outputs
            PWMB7_DB_reg    <= T3PWM and not counter_en;
            PWMB8_DB_reg    <= not T3PWM and not counter_en;
        end if; -- if rising_edge(CLKOUT)
    end process;
        
END identifier;

When it is in its own project, the timing simulation would show that it's all good.

However, when I incorporate it into the big project, the timing simulation would fail, however the functional simulation shows that it does what its supposed to do.

Then I thought its a timing problem, but the compilation flow summary says all timing requirements have been met. So what's up?

Note: Within the failed timing simulation results, this thing doesn't stop counting and the counts are not normal, once in awhile it would jump to a number far away (not wraparound).

Thanks.

Altera_Forum · ‎03-25-2010

Have I asked a question that is unanswerable or are there so many duplicates of this problem that I should have searched for it first?

Thanks

Altera_Forum · ‎03-25-2010

Where does the clock CLK_OUT come from? Is it clean?

I think that you should remove EVBCONDB_reg from the sensitivity list and only leave the clock (and a reset input, if possible). You should update multiplier in the process under the line where you update EVBCONDB_reg.

I don't know how Quartus will synthesize this, but the simulator may execute several times the process after a rising edge of the clock, because of the changes in EVBCONDB_reg.

Altera_Forum · ‎03-25-2010

Thanks for replying, the EVBCONDB only gets changed once, during the initialisation of the system. So throughout the operation of this code, EVBCONDB should be regarded as a constant.

Altera_Forum · ‎03-25-2010

Oups sorry... I don't know why I thought that EVBCONDB was changing in the process...

If EVBCONDB is constant you can move the code that sets multiplier outside of the process.

How about CLK_OUT? Does it come from a pll, a clock input?

Altera_Forum · ‎03-25-2010

it comes from the DSP that is communicating with it. So I guess its from the oscillator within the DSP.

Altera_Forum · ‎03-25-2010

I'm surprised how Altera doesn't have any relevant complaints about the big design and its failing within the timing simulation.

Altera_Forum · ‎03-25-2010

After poking at Assignments -> Settings -> Simulator Settings -> Simulation Verification

tick enable on Setup and hold time violation detection.

I get this during 'timing simulations'


Warning: Found setup time violation at time 3198.98 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3198.98 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 3199.03 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 3199.16 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3205.64 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3205.64 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3205.64 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3205.64 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3212.31 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3832.25 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3832.25 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 3832.34 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3838.91 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3838.91 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3838.91 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 3838.91 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 3838.97 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 3839.06 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 5105.45 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 5105.55 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 5112.12 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 5112.12 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 5112.12 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 5112.12 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 5112.18 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 5112.25 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 5112.26 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 7658.53 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 7658.53 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 7658.53 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 7658.53 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 7658.59 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 7658.66 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 7658.68 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 9565.18 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 9565.18 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 9571.67 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 9571.67 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 9571.67 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 9571.67 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 9571.73 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 9571.81 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 9571.82 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 10198.28 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|PWMB7_DB_reg"
Warning: Found setup time violation at time 10198.28 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|PWMB8_DB_reg"
Warning: Found setup time violation at time 10198.28 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:prev_T3PWM"
Warning: Found setup time violation at time 10204.94 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 10204.94 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 10204.94 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 10204.94 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 10205.0 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 10205.09 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 11478.15 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 11484.81 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 11484.81 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 11484.87 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 11484.96 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 11485.0 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 11491.48 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 11491.48 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 11491.48 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12758.02 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12758.02 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 12758.08 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found hold time violation at time 12758.2 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12764.69 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12764.69 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12764.69 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12764.69 ns on register "|cpt_spi_to_mb|spi_to_bus_v5:inst2|\DB_T3PWM_proc:count"
Warning: Found setup time violation at time 12771.35 ns on register
...

Since the T3PWM and the clock coming from the DSP aren't always in sync/phase, should I have another DFF before sending the input into this block?

Altera_Forum · ‎03-25-2010

By the way, by your recommendation I've precalculated the count outside the process and surprisingly it has reduced the number of hold time and setup time violations. Still, there are some lingering around, what should I do about them?

Here is the new process


    DB_T3PWM_proc: process(CLKOUT)
    variable counter_en    : STD_LOGIC;
    variable prev_T3PWM    : STD_LOGIC;
    variable count    : UNSIGNED (8 downto 0);
    begin
    
        if(rising_edge(CLKOUT)) then
-- if we see a transition, start the clock and enable deadband
            if(prev_T3PWM /= T3PWM) then
                counter_en := '1';
                count := EVB_count;
            end if;
                
-- if we've reached 0, stop counting and disable deadband
            if(count = "000000000") then
                counter_en := '0';
-- else decrement counter by one
            else
                count := count - 1;
            end if;
-- remember T3PWM for next time
            prev_T3PWM := T3PWM;
-- and output delayed PWM outputs
            PWMB7_DB_reg    <= T3PWM and not counter_en;
            PWMB8_DB_reg    <= not T3PWM and not counter_en;
        end if; -- if rising_edge(CLKOUT)
        
        if falling_edge(CLKOUT) then
        end if;
    end process DB_T3PWM_proc;

Altera_Forum · ‎03-26-2010

I think that the synthesizer was a bit confused by the sensitivity list and didn't know how to synthesize your project.

Still it is strange that your design meets timing requirements and still fails in timing simulation... Are you sure that the inputs you use for your simulation follow the timing requirements that you gave? Do you have any unconstrained I/O paths?

Altera_Forum · ‎03-26-2010

What do you mean by that, I should say that the input is not synchronous with CLKOUT, so thus we might have setup violations.

Altera_Forum · ‎03-26-2010

Could you give a bit more details about your system? Is the input serial or parallel? If your logic is synchronized on clkout but not the input, did you include synchronization stages to avoid metastability issues?

Altera_Forum · ‎03-26-2010

Input is serial and all I care is if its changing. That's it.

And whenever the input changes, I want to start the clock. That's it.

How to handle the metastability problem? I don't know. Thanks for helping me out

Altera_Forum · ‎03-26-2010

What do you mean by "start the clock"?

Have a look at this document (http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf) from Altera that explains a few things about metastability. I think you should create a false path on your input signal in your timing requirements, so that Quartus doesn't have to try to meet any setup/hold requirements you don't need, and add a two registers chain between the input and your logic. Have a look at figure 3, and imagine that "Clock 2 domain" is your logic in the FPGA, and "clock 1 domain" is the signal source outside the FPGA.

Altera_Forum · ‎03-26-2010

--- Quote Start ---

Input is serial and all I care is if its changing. That's it.

And whenever the input changes, I want to start the clock. That's it.

How to handle the metastability problem? I don't know. Thanks for helping me out

--- Quote End ---

And whenever the input changes, I want to start the counter.

My bad.

The algorithm is:

1. look for a edge change in T3PWM (0->1 or 1->0)

2. start the counter

3. after the count decrements to 0, stop counter.

I'll read the document. Thanks.

Altera_Forum · ‎03-26-2010

I've understood the problem, however I am having trouble finding vhdl code (yes, seriously) to synthesize this synchronizer circuit, could someone please help me.

Altera_Forum · ‎03-26-2010

I've managed to build a synchronizer and have it verified by the RTL viewer. Now, how do I set the simulation to simulate that first flip flop to have a setup and hold time of 0 ns?

Why am I doing that? We'll thats the advice from one the threads I read about simulating these synchronizers.

Altera_Forum · ‎03-29-2010

You can set the input as false path in Timequest. If you use synchronizers you don't need to have any specific set up and hold times.