Simulation in Quartus II

Altera_Forum · ‎07-31-2009

hello friends,

I am a beginner in Quartus. In my project I am trying to do simulation using Quartus II for my verilog code.

I have top level module cpu_io and the other one is my test module. From my understanding, in order to simulate it is essential that those signals should be defined in the portlist.

So, in the top- level entity or the top level file I have the portlists defines as:

cpu_io u0

{

...

portlist for cpu

...

};

testmodule u2

{

..

portlist for testmodule (these include the signals for which I want to see the simulations)

..

};

After I compile, generate the netlist and try to insert new node in the vector waveform file.The list of all pins does not include the pins for the testmodule :confused:

Am I doing something wrong?

I went through the documanetation couple of times but was not able to figure out. :(Could you guys please help me.. Thanks

Regards,

sim

Altera_Forum · ‎07-31-2009

Hi,

Your problem is "SOME" of the pins are not visible in node finder.

If you are going for timing simulation then internal signals may not appear in the node finder. To see how they function you can go for functional simulation for which you will have to do generate functional simulation netlist. If you want to see them in timing simulation you have to define them as as input/output signal for testing purposes.

Another option is in the node finder filter instead of selecting Pins(All) select Design Entry (All Names). They can be customized also.

Altera_Forum · ‎07-31-2009

--- Quote Start ---

Hi,

Your problem is "SOME" of the pins are not visible in node finder.

If you are going for timing simulation then internal signals may not appear in the node finder. To see how they function you can go for functional simulation for which you will have to do generate functional simulation netlist. If you want to see them in timing simulation you have to define them as as input/output signal for testing purposes.

Another option is in the node finder filter instead of selecting Pins(All) select Design Entry (All Names). They can be customized also.

--- Quote End ---

Hi,

are all of your ports missing ? Did you get any messages like "input stuck to GND" during the synthesis ? That could be a hint that you have an error in your source code and the block is removed during synthesis.

Kind regards

GPK