So simple it's stupid: RS232 Receive Module works in Modelsim, fails in DE2-115

[Altera_Forum]

Hi. So, I am using Quartus II 12.1 sp1 and a DE2-115 board. I am running the clk at 100 MHz; at the top level it goes through a PLL to generate the 100 MHz clk. At the top level I am putting the data and rx_state on LEDs as well as the 7-seg display. I know the 7-seg display works 100%. Whenever I send a 1 via hyperterminal I get "0000_0001" displayed on the LEDs, which is wrong.  

 So, I have 2 questions.  1. Do you see a flaw in my state machine / code? 2. How do I verify that my circuit is passing timing? I am used to putting timing constraints on the main clock in Xilinx UCFs. Is it that simple in Quartus? I've looked into using TQ and it seems a bit over kill for a simple timing constraint.   Thanks, -Joe

[Altera_Forum]

module rs232 ( input clk, input reset, input rxd, output txd, output debug, output data_out, output nd_out, //output fr_q, //input fr_rdclk, //output fr_empty, //input fr_rdreq, input ft_data, input ft_wrclk, output ft_full, input ft_wrreq ); // These Values assume a 100 MHz clock with a period of 10 ns. // Assume 115200 baud. Each bit is 1/115200 or 8.7uS. 8.7 us / 10 ns = //parameter v_fullhalfbit = 651, v_fullbit = 434; //50 MHz parameter v_fullhalfbit = 13'd1302, v_fullbit = 13'd868; //100 MHz fifo_16x64 fifo_txd_inst ( .aclr(reset), .data(ft_data), .rdclk(ft_rdclk), .rdreq(ft_rdreq), .wrclk(ft_wrclk), .wrreq(ft_wrreq), .rdempty(ft_empty), .wrfull(ft_full), .q(ft_q) ); metafilter metafilter_inst ( .clk(clk), .reset(reset), .sigin(rxd), .sigout(rxd_m), .rise(rxd_rise), .fall(rxd_fall) ); // Begin Transmit FSM always @ (posedge clk or negedge reset) begin if (!reset) begin //q1 <= 0; //q2 <= 0; end else begin end end // End Transmit FSM // Begin Receive FSM //wire data_out_i //wire rxd_m, rxd_rise, rxd_fall; reg rx_data, data_out_i; //reg nd_out_i; reg rx_state, rx_ns; reg rx_c_fullhalfbit, rx_c_fullbit; reg rx_c_eight; parameter rx_idle = 4'd0, rx_start = 4'd1, rx_rec = 4'd2, rx_stop = 4'd3; assign txd = 1; assign data_out = data_out_i; //assign data_out_i = (rx_state == rx_stop & rx_c_fullbit == 0) ? rx_data : data_out_i; assign nd_out = (rx_state == rx_stop & rx_c_fullbit == 0); assign debug = {rx_c_fullhalfbit, rx_c_eight}; // Begin Next State Logic always @ (posedge clk or negedge reset) begin if (!reset) begin rx_state <= rx_idle; //rx_ns <= rx_idle; end else rx_state <= rx_ns; end always @* begin case (rx_state) rx_idle: if (rxd_fall) rx_ns = rx_start; else rx_ns = rx_idle; rx_start: if (rx_c_fullhalfbit == 1'd0) rx_ns = rx_rec; else rx_ns = rx_start; rx_rec: if (rx_c_eight == 4'd7 && rx_c_fullbit == 0) rx_ns = rx_stop; else rx_ns = rx_rec; rx_stop: if (rx_c_fullbit == 0) rx_ns = rx_idle; else rx_ns = rx_stop; default: rx_ns = rx_idle; endcase end // End Next State Logic // Begin Output Logic always @ (posedge clk or negedge reset) begin if (!reset) begin rx_c_fullhalfbit <= v_fullhalfbit; rx_c_fullbit <= 0; rx_c_eight <=4'd0; rx_data <= 8'd0; data_out_i <= 1'b0; end else begin case (rx_state) rx_idle: if (rx_c_fullhalfbit == 0) rx_c_fullhalfbit <= v_fullhalfbit; rx_start: if (rx_c_fullhalfbit == 0) rx_c_fullhalfbit <= v_fullhalfbit; else rx_c_fullhalfbit <= rx_c_fullhalfbit - 1; rx_rec: if (rx_c_fullbit == 0) begin rx_c_fullbit <= v_fullbit; //rx_data <= {rx_data, rxd_m}; rx_data <= rxd_m; rx_c_eight <= rx_c_eight + 4'd1; if (rx_c_eight == 4'd7) rx_c_eight <= 0; end else begin rx_c_fullbit <= rx_c_fullbit - 1; end rx_stop: if (rx_c_fullbit == 0) begin rx_c_fullbit <= v_fullbit; data_out_i <= rx_data; end else begin rx_c_fullbit <= rx_c_fullbit - 1; data_out_i <= data_out_i; end endcase end end // End Output Logic endmodule

[Altera_Forum]

Solution: Didn't specify bus width at the top level and so it was reduced to an implicit net of 1 wire.