Some blocks are not synthesized

[Altera_Forum]

I have the following top level file which is in the form of a block diagram 

 http://www.alteraforum.com/forum/attachment.php?attachmentid=9502&stc=1   it consists of the following modules namely:  http://www.alteraforum.com/forum/attachment.php?attachmentid=9503&stc=1   but when I try to compile it, not all modules where use? why? (the number of logic cells used is so low, so it implies that there are modules that fail to synthesize)  http://www.alteraforum.com/forum/attachment.php?attachmentid=9504&stc=1   Why? How do we fix this? Thanks :-P

[Altera_Forum]

The image is not very clear, but do you have a lot of unconnected signals? It looks like you do from the picture. Unconnected signals can mean logic is removed because it is unused.

[Altera_Forum]

why not post some of your code or error/warning messages. 

And maybe a clearer pciture?

[Altera_Forum]

@Tricky 

 attached is the Quartus project... One module (named memory_arbiter) gets synthesized even if there are missing wire connections.. The other modules still do not appear in the 'Resource utilization by entities' inside the 'Analysis and Synthesis Compilation Report'   PS: if we try to compile, we get the following a successful message, but if we try to view the resource utilization, several modules were left out namely : 'camera_write', 'sobel', 'gaussian', 'thinning'