Some commands that worked at ModelSim do not work at QuartusII

[Altera_Forum]

Hi, 

  In order to explore the features of ModelSim, I successfully compiled some examples present in the tutorial folder.  However, I willed to synthesize one of these projects at QuartusII, but failed at the following line:  @(posedge clk) while (rdy != 0) @(posedge clk) ;  ...returning this error:    --- Quote Start ---  loop with non-constant loop condition must terminate within 250 iterations  --- Quote End ---    Although I noticed at the Web the same message above on various posts, I could not find any one whose reason is similar to that command sequence. Could someone give a tip ?   Thanks in advance.

[Altera_Forum]

while and for loops create one instance of hardware for every iteration. The number of iterations must be known at compile time. you want to code this as always @(posedge clk) if (rdy == 0) ...

[Altera_Forum]

But the piece of the code above is at the middle of an always block. 

Is there some alternative to replace that ?   I´m assuming that I can´t insert an always block inside another.

[Altera_Forum]

Remember that verilog and vhdl aren't software, they generate hardware. To do something at the first clock edge when rdy is 1 use: always @(posedge(clk)) begin if (rdy == 1) stuff to do goes here endif end  

This will synthesize into what I think you are after.

[Altera_Forum]

hi Galfonz, 

  I replaced the original line bellow, not buildable by compiler ... @(posedge clk) while (rdy != 0) @(posedge clk) ; ...for the following, that supposedly would synthesize something with a same behavior: always @(posedge(clk)) // error pointed to this line begin if (rdy == 1) @(posedge clk) endif // also tried end end but now I got the following error:   --- Quote Start ---  Verilog HDL syntax error at proc.v(55) near text "always"; expecting "end"  --- Quote End ---    There are another way to replace the original @(...)while...@(...) sequence for another one more compatible with various compilers ?

[Altera_Forum]

The difference between both tools is (in simplified view): 

Modelsim is simply interpreting HDL code line-by-line, it has no limitations to act on multiple clock inputs or perform endless iteration loops, except those set by computer memory and execution time.   A synthesis tool needs to map Verilog or VHDL syntax to hardware, combinatorial logic and flipflops. You must be aware of the fact that only part of the language constructs that can be written in Verilog or VHDL is actually accepted for hardware synthesis.   The nested @(posedge clk) construct can't be mapped to hardware, with or without the if condition.    --- Quote Start ---  There are another way to replace the original @(...)while...@(...) sequence for another one more compatible with various compilers ?  --- Quote End ---    Probably. But we need an example with an actually executed statement, e.g. a variable assignment to suggest an equivalent construct. Preferably a "full design" with inputs and outputs.  Instead of explaining in detail why the examples aren't synthesizable, I suggest to use the Verilog language templates offered in the context menu of the Quartus editor as a starting point. A clocked design that waits for some input signals can be best coded as a finite state machine, at least the non-trivial cases.

[Altera_Forum]

I should have made it clear that you can't ever nest a @(...) construct inside another. The @() is almost always "always @(some_clock_edge) begin <code> end" For best performance <code> should be something that can be done in 1 or 2 levels of logic. It doesn't make sense to say "when there is a clock edge, wait for a clock edge." like your code would imply. To do what you seem to have in mind in your original post, you can check that rdy is high (or low) when there is a clock edge as I've written above.

[Altera_Forum]

Hello, 

  Thank you both very much for the pretty enlightening explanation. I did not realize up to now that the Modelsim "variant" of Verilog compiler do not aim to necessarily give support for synthesis, but simulation, what in fact makes all sense, once it can deal with a wide range of nested commands, as the one above.  What indeed happened is that I took a sample example verilog project available at the tutorial folder of Modelsim, composed of a code and obviously its associated testbench, and my expectation was to find not so much errors as noticed.  What I suppose to be the correct procedure is to create a project in the tool of the manufacturer (Altera, in this case), and afterward use the Modelsim just as an 'advanced tool' due at this sequence the chance to face to some inconsistency at language will be reduced, it´s right ?

[Altera_Forum]

I'd recommend you look at some textbooks and internet tutorials on synthesizable Verilog and make sure you have a good understanding on what constructs can be used in hardware. Use the templates available in Quartus as suggested by FvM. Simulators like Modelsim implement constructs that can't be synthesized because they are useful in making a test bench. Its much faster to develop using a simulator than the hardware tools. For a non-trivial project, I'd recommend making sure it simulates correctly before taking it to hardware. Just make sure you understand how to write code that can be synthesized.