Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Some problems with SOPC builder

Altera_Forum
Honored Contributor II
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I don't know if you have the following issues with the SOPC builder. 

 

1. Within the SOPC builder, you can use the pll or Avalon altpll component. When I select the "pll" component, I am uable to configure it. When I use the altpll component, even if I don't tick the box, Create "locked" output, I still have a "locked_from_the altpll_0" output on the instance symbol in the Quartus-II after I generate the sopc. 

 

2. When I create a custom component with the SOPC builder, create an avalon_tristate_slave and create a clock port, the SOPC builder always creates two avalon_tristate_slaves and two clock ports. I can't delete the redundant avalon_tristate_slave and redundant clock port. It always gives warning message. 

 

Quartus-II 9.0 sp1 web edition is installed within Window's XP sp3.
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Altera_Forum
Honored Contributor II
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My question "within the SOPC builder, you can use the pll or Avalon altpll component. When I select the "pll" component, I am uable to configure it" is answered by "QII 7.2SP3 SOPC Builder - Cannot modify PLL module?" in this forum because I have a space in the name of my project directory.

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Altera_Forum
Honored Contributor II
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Be sure that signals not belonging to avalon-slave-tristate or avalon-clock are configured as "export" in a "condit_end" interface, then remove interfaces without signals.

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Altera_Forum
Honored Contributor II
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Thanks, parrado. 

 

There are no other signals which do not belong to avalon-slave-tristate or avalon-clock.
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Altera_Forum
Honored Contributor II
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Could you post the component HDL file and SOPC system screenshot?

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