Speed up Gate-level simulation

[Altera_Forum]

Hi, 

 I am running a gate-level simulation to try and verify my design but its taking a very long time. Is there a way I can speed this process up? I don't think multithreading is a possibility... The only option I have at the moment is to break the design into small sections which will require me to write more testbenches to ensure each part of the design is initialized correctly/provided with the correct operational data - which I'm not against doing if it will speed up the simulation...  One thing I had wondered about was if it was possible to get modelsim to dump results into a file and not put signals into the GUI?  All suggestions welcome  David

[Altera_Forum]

The biggest thing will be upgrading your modelsim licence. The cheaper the licence, the slower it runs. Or even move to Linux (this runs much faster). 

 Gate level sims always take a long long time. The best way to speed them up is to do as much testing at the RTL level as possible.

[Altera_Forum]

does your testbech take a long time to complete the simulation? For example, if you try to simulate 50000000 clock cycles, your computer resources collapse.

[Altera_Forum]

I am running a full license version of Modelsim Altera on Windows. So trying to use Linux could be a possibility. I have the design fully operational under RTL simulation. I just need to be sure there aren't any post synthesis surprises or huge propagation delays. 

 To bertulus, yes, the simulation takes a long time to complete - in fact it hasn't yet, not even close. Part of the problem is that it needs to run over a very long time (ms). RE computer resources, memory usage is high but I have spare and its only using one processor core so although its using that pretty much to the limit, its not crashing my PC or anything. Leaving it to run isn't an option as it will just take too long.  I have access to Signaltap, what about running the code on the FPGA and trying to view the signals using this?

[Altera_Forum]

When I meant upgraded licence, I meant like getting PE, SE, DE versions or even Questa. Each one runs faster than the previous. leaving it overnight/weekend might be your only option for a long simulation run. 

 And why are you expecting huge propagation delays? havent you constrained the design with timequest?  You could try putting it on the board, but signaltap will only give you limited visibility.

[Altera_Forum]

Just a quick correction. All versions of Modelsim/Questa above Modelsim PE run as the same speed if you have all available optimizations on. 

 You should be able to log signals to a file at the beginning of the simulation add the to the wave window at the end of simulation and then scroll back to see waveform throughout the simulation.

[Altera_Forum]

Hi,  

 Thanks for the replies. For now I am trying to split the design up and test the 3 main components separately. This has a number of advantages in that I can run multiple instances of Modelsim and therefore simulate all three components at once. Each of the 3 broken down designs is considerably smaller as in each case the signals relating to the other two components are removed - only one component is ever operational at any time in the complete design anyway. With Modelsim Altera simulation optimization is not supported, one other idea from Altera support would be to disable signal logging in the wlf file until the time of interest.... I'll let you all know how I get on.