Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,079 Views

Starting an HPS simulation fails due to shared library error.

I have a simulation model of a Cyclone5 HPS, which was generated by a Qsys project. I am trying to start the simulation on my Linux machine. I get the following output: 

 

vsim -mvchome /tools/intelFPGA/17.0/ip/altera/mentor_vip_ae/common -t ps -L work -L work_lib -L altera_common_sv_packages -L border -L merlin_axi_slave_ni_0_altera_axi_master_id_pad -L hps_io -L fpga_interfaces -L rst_controller -L mm_interconnect_0 -L merlin_axi_slave_ni_0 -L hps_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev hps# vsim -mvchome /tools/intelFPGA/17.0/ip/altera/mentor_vip_ae/common -t ps -L work -L work_lib -L altera_common_sv_packages -L border -L merlin_axi_slave_ni_0_altera_axi_master_id_pad -L hps_io -L fpga_interfaces -L rst_controller -L mm_interconnect_0 -L merlin_axi_slave_ni_0 -L hps_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev hps # Start time: 18:47:58 on Jun 21,2017# Loading /tmp/u@pc_dpi_20624/linuxpe_gcc-7.1.1/export_tramp.so# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading ieee.numeric_std(body)# Loading work.hps(rtl)# Loading hps_0.hps_hps_0# Loading sv_std.std# Loading fpga_interfaces.QUESTA_MVC# Loading fpga_interfaces.mgc_axi_pkg# Loading altera_common_sv_packages.verbosity_pkg# Loading altera_common_sv_packages.avalon_mm_pkg# Loading fpga_interfaces.hps_hps_0_fpga_interfaces_sv_unit# Loading fpga_interfaces.hps_hps_0_fpga_interfaces# Loading fpga_interfaces.mgc_axi_slave_sv_unit# Loading fpga_interfaces.mgc_axi_slave# Loading fpga_interfaces.mgc_common_axi_sv_unit# Loading fpga_interfaces.mgc_common_axi# Loading fpga_interfaces.altera_avalon_reset_source# Loading fpga_interfaces.altera_avalon_clock_source# Loading hps_io.hps_hps_0_hps_io# Loading border.hps_hps_0_hps_io_border_sv_unit# Loading border.hps_hps_0_hps_io_border# Loading border.hps_hps_0_hps_io_border_memory# Loading merlin_axi_slave_ni_0.altera_merlin_axi_slave_ni# Loading merlin_axi_slave_ni_0.altera_merlin_address_alignment# Loading merlin_axi_slave_ni_0.altera_merlin_burst_uncompressor# Loading merlin_axi_slave_ni_0.altera_avalon_sc_fifo# ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim.# Loading mm_interconnect_0.hps_mm_interconnect_0# Loading merlin_axi_slave_ni_0_altera_axi_master_id_pad.altera_merlin_axi_translator# Loading rst_controller.altera_reset_controller# Loading rst_controller.altera_reset_synchronizer# ** Warning: (vsim-3934) hps/simulation/hps.vhd(636): - Missing VHDL connection for formal Verilog port 'buser'.# Time: 0 ps Iteration: 0 Instance: /hps/merlin_axi_slave_ni_0 File: hps/simulation/submodules/altera_merlin_axi_slave_ni.sv# ** Warning: (vsim-3934) hps/simulation/hps.vhd(636): - Missing VHDL connection for formal Verilog port 'ruser'.# Time: 0 ps Iteration: 0 Instance: /hps/merlin_axi_slave_ni_0 File: hps/simulation/submodules/altera_merlin_axi_slave_ni.sv# ** Warning: (vsim-3015) hps/simulation/submodules/hps_mm_interconnect_0.v(157): - Port size (1) does not match connection size (64) for port 's0_wuser'. The port definition is at: hps/simulation/submodules/altera_merlin_axi_translator.sv(160).# Time: 0 ps Iteration: 0 Instance: /hps/mm_interconnect_0/merlin_axi_slave_ni_0_altera_axi_master_id_pad File: hps/simulation/submodules/altera_merlin_axi_translator.sv# ** Warning: (vsim-3015) hps/simulation/submodules/hps_mm_interconnect_0.v(157): - Port size (1) does not match connection size (64) for port 'm0_ruser'. The port definition is at: hps/simulation/submodules/altera_merlin_axi_translator.sv(240).# Time: 0 ps Iteration: 0 Instance: /hps/mm_interconnect_0/merlin_axi_slave_ni_0_altera_axi_master_id_pad File: hps/simulation/submodules/altera_merlin_axi_translator.sv# ** Warning: (vsim-3015) hps/simulation/submodules/hps_mm_interconnect_0.v(157): - Port size (1) does not match connection size (64) for port 'm0_buser'. The port definition is at: hps/simulation/submodules/altera_merlin_axi_translator.sv(219).# Time: 0 ps Iteration: 0 Instance: /hps/mm_interconnect_0/merlin_axi_slave_ni_0_altera_axi_master_id_pad File: hps/simulation/submodules/altera_merlin_axi_translator.sv# Compiling /tmp/u@pc_dpi_20624/linuxpe_gcc-4.7.4/exportwrapper.c# ** Fatal: ** Error: (vsim-3828) Could not link 'vsim_auto_compile.so': cmd = '/tools/intelFPGA/17.0/modelsim_ase/gcc-4.7.4-linux/bin/gcc -shared -fPIC -m32 -o "/tmp/u@pc_dpi_20624/linuxpe_gcc-4.7.4/vsim_auto_compile.so" "/tmp/u@pc_dpi_20624/linuxpe_gcc-4.7.4/exportwrapper.o" '# (vsim-50) A call to system(/tools/intelFPGA/17.0/modelsim_ase/gcc-4.7.4-linux/bin/gcc -shared -fPIC -m32 -o "/tmp/u@pc_dpi_20624/linuxpe_gcc-4.7.4/vsim_auto_compile.so" "/tmp/u@pc_dpi_20624/linuxpe_gcc-4.7.4/exportwrapper.o" >'/tmp/questatmp.8YlULA' 2>&1) returned error code '1'.# The logfile contains the following messages:# /lib/crti.o: file not recognized: File format not recognized# collect2: error: ld returned 1 exit status# # No such file or directory. (errno = ENOENT)# # # FATAL ERROR while loading design# Error loading design# End time: 18:47:59 on Jun 21,2017, Elapsed time: 0:00:01# Errors: 1, Warnings: 6  

 

My environment uses gcc 7.1.1 and I have Quartus Lite 17.0 and free Modelsim Intel Edition running. Is the gcc of my environment too new?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
104 Views

Instead of gcc 4.7.4, I used the latest gcc on my distribution, which enabled me to see the real error message. Apparently you need a Questa Verification IP (VIP) license to simulate bus functional model (BFM) components. This means that you cannot simulate a Qsys generated HPS project using the Modelsim version which is integrated in the Quartus Lite package. Further support from Intel also revealed that the simulation model generated by the Qsys is only a simplified bus model, which does not accurately model the HPS along with the peripherals that you have created, but only some dummy transactions to model the HPS-FPGA bridge.

Reply