Hi,I designed a state machine in my verilog codes. I evaluate it in the DE2-115 board, and everything looks good. When I opened the state machine viewer in the Quartus II 12.0, however, it shows all the nodes but no transitions or transition conditions are shown. Can anyone help to explain why this is the case? Is there anything wrong? Thanks, -Roger always @(posedge clock or negedge reset_n) begin if (~reset_n) begin cs <= stIdle; end else begin case (cs) stIdle : begin DataWindow <= 1'b0; ReadWindow <= 1'b0; Done <= 1'b0; index_write <= 0; index_read <= 0; if (start) begin Done <= 1'b0; cs <= stLoadData; end end stLoadData : begin DataWindow <= 1'b1; cs <= stLoopWrite; end stLoopWrite : begin index_write = index_write + 1; if (index_write == read_length) begin DataWindow = 1'b0; cs = stReadData; end end stReadData : begin ReadWindow <= 1'b1; cs <= stLoopRead; end stLoopRead : begin index_read = index_read + 1; if (index_read == read_length) begin ReadWindow = 1'b0; cs = stDone; end end stDone : begin Done <= 1'b1; if (~start) begin cs <= stIdle; end end default : begin cs <= stIdle; end endcase end end
Don't know about that, but why do you mix blocking (=) and non-blocking (<=) assignments in your code?That is really bad coding practice and can lead to numerous subtle simulation vs implementation errors. I would recommend you change all the blocking to non-blocking assignments. It may also be why the tool can't detect the state transitions, but I'm just guessing on that.