Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

State minimization

Altera_Forum
Honored Contributor II
1,782 Views

Hello all. 

 

I am wondering if Quartus ii performs any state minimization, and if so, how is it used/enabled? 

 

Thank you
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
878 Views

Do you explicitly mean states, or logic?  

State machines are encoded using one of several methods. Grey code, one hot and counter. By default it will encode 1 hot. Minimization can occur during synthesis
0 Kudos
Altera_Forum
Honored Contributor II
878 Views

 

--- Quote Start ---  

Do you explicitly mean states, or logic?  

State machines are encoded using one of several methods. Grey code, one hot and counter. By default it will encode 1 hot. Minimization can occur during synthesis 

--- Quote End ---  

 

 

I mean eliminating redundant states.  

 

Thank you very much for your time
0 Kudos
Altera_Forum
Honored Contributor II
878 Views

Assuming you mean states that cannot be entered, it might depend on the encoding scheme as to whether they are removed or not. The syntheses will remove any redundant logic.

0 Kudos
Reply