I have a particular synchronization chain in my design where the timing is very tight and Quartus (10.0 SP1) has chosen to perform register duplication on the final stage of it, effectively decreasing the chain length by 1. Does anyone know of a way to stop it from doing this? The chain's length is 3 and I have already set the Synchronization Register Chain Length option to 3 in Analysis & Synthesis settings. I also tried 2 and 4 but the result is the same.In case it matters, my target device is a Cyclone II.
What you can do is apply an assignment specifically to your register chain that prevents Quartus from performing duplication. You can make this setting either in the Assignment Editor, directly in the QSF, or by applying an attribute to the register within your HDL code.See the Quartus QSF settings reference manual on page 6-228: http://www.altera.com/literature/manual/mnl_qsf_reference.pdf Specifically the assignment you will make will look something like: set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION -to <to> -entity <entity name> <value> However, duplicating the final stage of a chain does not reduce the length of the chain. You now effectively have two chains each with a length of 3 and each feeding different logic. Jake
Thanks, that did it!To clarify my reasoning, the usual definition of a synchronization chain says that all registers in the chain except the last one must have fanout of 1. By doing register duplication on the last stage, the second-last stage ends up with fanout of 2, so it's not a standard synchronization chain anymore. In principle if the value in stage 2 was still metastable then the replicated final stages could take on different values, potentially causing design failure. Granted, it is extremely unlikely since by stage 2 a metastable value is probably close enough to either 1 or 0 that all replicated registers will resolve it to the same thing, but I don't want to take any chances. :)