Strange warnings in quartus 2

[Altera_Forum]

I have a system in which I am trying to run program code from sdram through sdram controller on the DE2 board. The clock signal for the SDRAM is generated from a clock signal output of PLL with phase shift of -3ns. After compiling I get the following strange warnings 

 Warning: Tri-state node(s) do not directly drive top-level pin(s)  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[15]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[15]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[14]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[14]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[13]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[13]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[12]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[12]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[11]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[11]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[10]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[10]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[9]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[9]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[8]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[8]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[7]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[7]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[6]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[6]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[5]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[5]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[4]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[4]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[3]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[3]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[2]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[2]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[1]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[1]" into an OR gate  Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[0]" to the node "first_nios2_system:inst|sdram:the_sdram|za_data[0]" into an OR gate   What do these strange warnings mean? Could they be the reason for my verify failed messages when I try to run program code? Help please!!  Chase

[Altera_Forum]

are your SDRAM pins connected directly from the SOPC Builder instantiation to pins on the top level of the design?

[Altera_Forum]

Yes the output lines from the SDRAM controller are connected to the corresponding output pins. I also get a warning about the SDRAM_CKE pin being stuck at VCC when it is also directly connected from the SOPC generated system to the SDRAM_CKE output pin. I have no clue what could be causing it. I will post my schematic later on when I get the chance.