Stratix 10 Programmer failure

[cmautner]

I am trying to program a STRATIX10TX SIGNAL INTEGRITY development kit. I had created my first .jic file and it went through 100% programming cycle. Then it started to go through a second pass of programming and failed at 1%. I don't know why it went through more than one pass.

After that happened I haven't been able to program it with the .soc files I was previously downloading successfully or the .jic file that failed originally.

I am using Quartus Prime Pro 20.4. Attached is an image of the failed Programmer window.

The Quartus error messages are listed below

Info(209060): Started Programmer operation at Wed Apr 16 16:25:42 2025
Info(18942): Configuring device index 2
Error(18939): Unexpected error in JTAG server: Timeout
Error(18939): Unexpected error in JTAG server: Timeout
Error(18952): Error status: Synchronization failed
Error(209012): Operation failed
Info(209061): Ended Programmer operation at Wed Apr 16 16:25:45 2025

[Fakhrul]

Hi,

There's a few question to clarify this issue:

1. Have you tried to power cycle?
2. Make sure the JTAG communication cable(s) are securely connected to the target system and are set to use a JTAG TCK frequency that is supported by all the devices in the JTAG chain and the target system, and the correct device is selected. Then retry the operation.
3. Have you try to program other working FPGA on the board to see if it was program successfully? This is to see if the the board is working fine or not.

Regards,

Fakhrul

[cmautner]

Hi Fakhrul, thanks for replying

1. I have power cycled many, many times. No success ever

2. The JTAG cable is really just a USB B cable that plugs into the port on the board. When it's plugged in Windows Device Manager shows an Altera USB-Blaster II. The JTAG frequency I'm trying now is 6MHz which is what we use on other boards of the same model successfully. I did use 24MHz the first time and we think that may be what fried the board

3. I don't know how to program any other FPGAs on the board. My understanding is that the other FPGA is just there to coordinate the code download for the Stratix 10. When I use the Quartus Programmer to Auto Detect it shows both devices but when I actually try and program it I get "Error(18939): Unexpected error in JTAG server: Timeout"

[Matt_P]

Hello @Fakhrul 
@cmautner is following the attached JIC procedure.
I'm not seeing any issue within, though can you please review along with their 05/05 feedback as I look further in parallel?
Thank you,