Stratix 10 Transceiver toolkit

[SDe_J]

Hello Intel forums,

I'm trying to use the Transceiver toolkit on my Stratix 10 GX H-tile devkit, but I'm having problems making it work. I'm following this video for instructions:

https://www.youtube.com/watch?app=desktop&v=bwhyJuphy8I

This tutorial seems to be for Quartus 18.1, but I'm using 22.4.

I have implemented a 25GBps transceiver with these settings in the dynamic reconfiguration tab:

I'm not sure if the "Use AVMM clock and reset ports only" is correct. If that's not selected, there's a bunch of ports that I don't know how or what to connect to.

In the ATX pll, I use these settings:

I connect the `reconfig_clk` ports on both IPs to a 100MHz clock and the reset to my global reset (not sure if this is correct; it's not mentioned in the video). After successfully compiling the design and programming the board, I opened the "System debugging toolkits" (the transceiver toolkit seems to not be seperate anymore.) and loaded my design there. Here's what I see:

From what I can tell, the system console can connect to the device, but it can't communicate with the PHY. Do I need a NIOS for this? I'd prefer to do without if possible.

Can you help me solve this? I'd like to produce eye diagrams for my transceiver as well as get the BER and optimum analog settings for my implementation.

If it's helpful, I can provide a qar archive of my project.

Thank you for your assistance.

[ZiYing_Intel]

Hi,

Can you provide the .qar file? So that I can try debug the issue from my side.

Typically, the clock and reset will be the main factor that cause this ttk issue.

Best regards,

zying

[SDe_J]

Hello Zying,

Thank you for your response. See the attached archive. It was created using Quartus 22.4.

[ZiYing_Intel]

Hi,

I found that your design compilation was fail. Please make sure your design was compiled successfully, then can proceed to the programmer and system console.

Best regards,

zying

[SDe_J]

Ah, my mistake. Attached to this message is a new qar archive that I confirmed works.

The transceiver IPs are instantiated in "interlaken_MGT.vhd".

The top level entity is in "4.._fpga_target_hw_devkit_s10_devkit_top_ent.vhd", but the architecture is in a separate file: "interlaken_MGT_arch.vhd"

Thank you again for helping me!

[SDe_J]

Hello Zying,

Have you had a chance to look at this design?

[ZiYing_Intel]

Hi,

The same issue also seen from my side. I am might need some times to debug the issue. Many I know you are using which .tcl file?

Best regards,

zying

[SDe_J]

Hi Zying,

I'm not using any .tcl file, as there was no mention of this in the video tutorial I watched.

[ZiYing_Intel · Accepted solution]

Hi,

I have a look into your IP design. I found that your IP design not meet below requirement. In the user guide, it has mentioned about that to enable Intel® Stratix® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

• Enable dynamic reconfiguration
• Enable Native PHY Debug Master Endpoint
• Enable capability registers
• Enable control and status registers
• Enable PRBS (Pseudo Random Binary Sequence) soft accumulators

For further information, you may refer to link below, Section 2.3.10, https://www.intel.com/content/www/us/en/docs/programmable/683621/current/dynamic-reconfiguration-parameters.html

Please do try enable the above options and compile the design again. Please do try run the system console again to see the error still exist anot.

Best regards,

zying

[SDe_J]

Hi Zying,

Thanks for pointing this out. This was indeed the problem. I am now able to use the transceiver toolkit.

Thanks again!

[ZiYing_Intel]

Hi,

Since your issue has been resolved, I am now close this thread. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Best regards,

zying