Stratix 2 Using PLL to generate clock for ADC and DAC

[Altera_Forum]

Hi! I'm using a Stratix 2 Development Board (ep2s60) and want to clock the ADC1 and DAC1 with my PLLs. 

The PLLs input clock is my internal 100MHz oscillator (pin AM17) and i want to generate an output clock in 125MHz. In the board schematic it seems like PLL5 (pin B15) should be used for the DAC (dac_PLLCLK1) and PLL11 (pin B18) should be used for the ADC (adc_PLLCLK1).  My problem is that it seems like quartus ii refuses to place my PLLs on PLL5 and PLL11. I have implemented two PLLs in "normal mode" using the MegaWizad (altpll) and connected their c0 output clocks to the dedicated PINS (?) for my required PLLs. My second PLL also feeds the rest of my system through the output s1. (See the attached picture with my design). My system seems to be clocked in 125 MHz but the ADC/DAC in 100 MHz. (I have moved the clock jumpers for the ADC/DAC to 1-2 on both J3 and J18) Both my PLLs is compensating for c0.  Does anyone know how i can "force" quartus to place my PLLs on PLL5 and PLL11?  All help would be really appreciated, banging my head over here..   some pll-related compilation warnings i get: Warning (12125): Using design file pll5.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project  Info (12023): Found entity 1: pll5 Warning (12125): Using design file pll6.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project  Info (12023): Found entity 1: pll6 Warning (332060): Node: sys_clk was determined to be a clock but was found without an associated clock assignment. Warning (332056): PLL cross checking found inconsistent PLL clock settings:  Warning (332056): Node: inst6|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000  Warning (332056): Node: inst5|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000  Warning (332056): Node: inst5|altpll_component|pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000 Warning (15058): PLL "pll6:inst6|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins Warning (15064): PLL "pll6:inst6|altpll:altpll_component|pll" output port clk[0] feeds output pin "adc_PLLCLK1" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Warning (15058): PLL "pll5:inst5|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins Warning (15064): PLL "pll5:inst5|altpll:altpll_component|pll" output port clk[0] feeds output pin "dac_PLLCLK1" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Warning (332056): PLL cross checking found inconsistent PLL clock settings:  Warning (332056): Node: inst6|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000  Warning (332056): Node: inst5|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000  Warning (332056): Node: inst5|altpll_component|pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000 Warning (332056): PLL cross checking found inconsistent PLL clock settings:  Warning (332056): Node: inst6|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000  Warning (332056): Node: inst5|altpll_component|pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000  Warning (332056): Node: inst5|altpll_component|pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000