Stratix-4 DDR3 dqs_n fitter error

[Altera_Forum]

Hi All, 

  I am using a Stratix-4 Dev. board and am trying to add a DDR3 UniPHY controller. All is fine until I get to the fitter which gives me the error:   error (176718): pin memory_mem_dqs_n[0] uses pseudo-differential output node rootport_fifo_qsys:u0|rootport_fifo_qsys_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0:p0|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_memphy:umemphy|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|rootport_fifo_qsys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiv:altdq_dqs2_inst|pseudo_diffa_0. however, these pins also have an i/o standard lvds that cannot be supported by the pseudo-differential output node.  I just can't understand this, Quartus generates the pinout automatically, right ? I have no control over the process other than tell it the type of memory hooked up to the controller. The pins are fixed by the PCB in advance. How does Quartus know which Dev. board pinout to assign the pins to? And then it generates the wrong pinout and gives me an error:mad:   Can someone enlighten me? Help me please !:oops:

[Altera_Forum]

I now know that you have to run the .tcl script generated by qsys called ...pin_assignments.tcl in Quartus > tools > tcl scripts. 

After that you are supposed to go to Assignment and edit the pins list to match your PCB...Xilinx does it so much simpler by letting you select a Dev. board as a template for your pins, etc. etc.

[Altera_Forum]

have you resolved this problem!?

[Altera_Forum]

--- Quote Start ---  have you resolved this problem!?  --- Quote End ---   Yes, it works now. Just make sure you run the .tcl script as I said above. You should also delete the incremental_db folder.  S.

[Altera_Forum]

Thx for the replay 

 The problem is that am getting this error before running the tcl script. I need to perform a correct full compilation before running the scrip in order to avoid wrong differential pairs.  e.g. while I have dqs[0] and this should have dqs_n[0] as differential pair, the script is ignoring it and it is creating another one dqs[0](n) and that is creating a confect!!  any ideas!?

[Altera_Forum]

--- Quote Start ---  Thx for the replay  The problem is that am getting this error before running the tcl script. I need to perform a correct full compilation before running the scrip in order to avoid wrong differential pairs.  e.g. while I have dqs[0] and this should have dqs_n[0] as differential pair, the script is ignoring it and it is creating another one dqs[0](n) and that is creating a confect!!  any ideas!?  --- Quote End ---    If you are using an Eval. board make sure that the .qsf file is correct for your version of design, i.e. if you are using a 230 board and the design is for a 530 board odd things may happen...  S.

[Altera_Forum]

Am using an DE4 230 board and the design am running is a uniPHY memory controller for external DDR2 memory which I have created with the megaWizard function. What I cant understand is that how come that there are errors from the auto generated code! The .qsf am using is the one generated by the wizard !! any hints!

[Altera_Forum]

Hi, 

 I have the same problem. Differential clock pair for external DDR3 interface should have ck and ck_n. However when doing the pin assignments it created another ck(n) and ck_n(n). Same also with dqs[1], dqs_n[1], dqs [0], dqs_n[0]... It created another dqs[1](n), dqs_n[1](n), dqs[0](n), dqs_n[0](n) when I want to do pin assignments. Is it a bug in QII 13.0? I have been stuck in here for days. Service request has not yet come back to me. Any idea what to do?

[Altera_Forum]

Hello again, 

 This is also the case for QII 12, 11 (on Windows) too. I have no clue what is the problem!!  I use to have such problems in the past and I was overcoming them by fully compiling the design then run the pin assignment script, but this time it is not working anymore since the compilation cannot be successfully completed.   The problem occurs by the auto-generated .qsf and therefore I am trying to check/fix it.   @arisrama22: What is the board u r using?

[Altera_Forum]

Hi, 

 I am using Cyclone V GT Development kit. Any way, I have not yet use this dev kit because I have problem with these DDR3 interfaces ck and dqs on pin assignments. Have not yet tried to do compiling either.  Regards

[Altera_Forum]

Hello, I have the same problem: after running the *pin_assignment.tcl, in pin planner are false differential pins *_ck[0](n) instead of *_ck_n[0] etc. Did somebody found the solution?

[Altera_Forum]

Dear arisrama22, 

 Do not make any assignment or add any pins before you make a 'analysis and synthesis' for you design then make a whole compilation after that should not have any problems.

[Altera_Forum]

--- Quote Start ---  Hello, I have the same problem: after running the *pin_assignment.tcl, in pin planner are false differential pins *_ck[0](n) instead of *_ck_n[0] etc. Did somebody found the solution?  --- Quote End ---     I have solved my problem. I had to make the following steps: 1. Generate the Qsys project 2. Run Analysis&Synthesis 3. Run the *_pin_assignments.tlc Script (the Pins will be wrong still wrong at this place), 4. Remove incremental_db 5. Make the full compilation of the project  As a result all pins will be correct and I could fit my design.