Stratix III 3SL150 Holes in Flash

Altera_Forum · ‎01-02-2012

I have the Stratix III 3SL150 DSP dev board and have a problem programming flash. Whenever I program the Intel CFI device, the flash ends up having large sections (on the order of 20 or 50 words) initialized to 0xFF but not actually programmed. I checked with some RTL that I wrote to operate slowly at 10x+ the read timings (e.g. 1 MHz for my FSM) and verified the errors that the Quartus software was giving me. I have been following the instructions in the board's user guide and reference manual perfectly with regards to jumper settings and software settings. I am using the stratixIII_3sl150_dev_pfl.sof file from the "factory recovery" archive downloaded from Altera's site. I have tried both USB+CPLD and external USB Blaster methods of programming and get the same results.

Am I doing something wrong, or does this appear to be a hardware problem?


*********************************************************
With the PFL pof file loaded, manually adding the CFI, and checking Program 
and Verify for all items: the FPGA pof and the sof containing Page 0, image.hex,
and OPTION BITS. Quartus II 11.0.
*********************************************************
Info: Started Programmer operation at Mon Jan 02 15:22:30 2012
Info: Configuring device index 1
Info: Device 1 contains JTAG ID code 0x121020DD
Info: Configuration succeeded -- 1 device(s) configured
Info: Device 1 CFI Flash 1 is PC48F4400P0VB00 (16 bits data bus)
Info: Erasing CFI Flash configuration device(s)
Info: Programming status: erasing flash device 1 (PC48F4400P0VB00) at device chain position 1
Info: Programming status: erasing flash memory at byte address 0x00000000
Info: Programming status: erasing flash memory at byte address 0x00008000
Info: Programming status: erasing flash memory at byte address 0x00010000
Info: Programming status: erasing flash memory at byte address 0x00018000
.
.
.
.
.
.
Info: Programming status: programming flash memory at byte address 0x03A90000
Info: Programming status: programming flash memory at byte address 0x03AA0000
Info: Programming status: programming flash memory at byte address 0x03AB0000
Info: Programming status: programming flash memory at byte address 0x03AC0000
Info: Programming status: programming flash memory at byte address 0x03FE0000
Info: Programming status: verify on flash device 1 (PC48F4400P0VB00) at device chain position 1
Info: Performing verification on device(s)
Error: Verify (address 0x03500000)  failure on device number 1
Error: Operation failed
Info: Ended Programmer operation at Mon Jan 02 17:12:51 2012
*********************************************************
In Quartus II 11.0, loading the PFL pof file, clicking Auto Detect, and checking Program 
and Verify only for image.hex and OPTION BITS.
*********************************************************
Info: Started Programmer operation at Mon Jan 02 17:34:37 2012
Info: Device 1 CFI Flash 1 is PC48F4400P0VB00 (16 bits data bus)
Info: Erasing CFI Flash configuration device(s)
Info: Programming status: erasing flash device 1 (PC48F4400P0VB00) at device chain position 1
Info: Programming status: erasing flash memory at byte address 0x03500000
Info: Programming status: erasing flash memory at byte address 0x03FE0000
Info: Programming device(s)
Info: Programming status: programming flash device 1 (PC48F4400P0VB00) at device chain position 1
Info: Programming status: programming flash memory at byte address 0x03500000
Info: Programming status: programming flash memory at byte address 0x03FE0000
Info: Programming status: verify on flash device 1 (PC48F4400P0VB00) at device chain position 1
Info: Performing verification on device(s)
Error: Verify (address 0x03500040)  failure on device number 1
Error: Operation failed
Info: Ended Programmer operation at Mon Jan 02 17:34:46 2012
*********************************************************
In Quartus II 8.0, attempting the last thing that I tried in Quartus II 11.0.
*********************************************************
Info: Started Programmer operation at Mon Jan 02 18:16:18 2012
Info: Device 1 CFI Flash is Intel 28F512P30 Bottom Boot (16 bits data bus)
Info: Erasing CFI Flash configuration device(s)
Info: Programming status: erasing flash memory at byte address 0x03500000
Info: Programming status: erasing flash memory at byte address 0x03FE0000
Info: Programming status: programming flash memory at byte address 0x03500000
Info: Programming status: erasing flash memory at byte address 0x03500000
Info: Programming status: reprogramming flash memory at byte address 0x03500000
Info: Programming status: erasing flash memory at byte address 0x03500000
Info: Programming status: reprogramming flash memory at byte address 0x03500000
Error: Operation failed
Info: Ended Programmer operation at Mon Jan 02 18:16:26 2012

All comments are appreciated. Thanks.

Altera_Forum · ‎01-03-2012

I managed to create a workaround. Several days ago, I tried to instantiate the PFL megacore. I was consistently getting the invalid silicon ID on device 1 error after the bitstream was loaded to the FPGA. This seemed to be to me a problem with the PFL core not recognizing the flash as it is two dies stacked on top of each other with no knowledge of each other. I went ahead and changed the parameters to make it a 256 Mbit flash (512 total on the package), pulled the highest address bit high, regenerated my pof as a 256 Mbit file with changed addressing (user space starting at byte 0x1500000 instead of 0x3500000), and programmed the device according to Altera's directions. This time, verification succeeded, I saw no more unexpected 0xFF gaps in the data, and my OR1200 CPU core now boots.

I'm still curious as to why this works and why it seems as though no one else on the web has had this problem.


module stratix_iii_flash_prog_top (
        input         pfl_flash_access_granted,
        input         pfl_nreset,
        output  flash_addr,
        inout   flash_data,
        output        flash_nce,
        output        flash_noe,
        output        flash_nwe,
        output        pfl_flash_access_request,
        output        sram_ncs,
        output        sram_noe
    );
    
    pfl pfl0 (
        .pfl_flash_access_granted(pfl_flash_access_granted),
        .pfl_nreset(pfl_nreset),
        .flash_addr(flash_addr),
        .flash_data(flash_data),
        .flash_nce(flash_nce),
        .flash_noe(flash_noe),
        .flash_nwe(flash_nwe),
        .pfl_flash_access_request(pfl_flash_access_request)
    );
    
    assign flash_addr = 1'b1;
    assign sram_ncs = 1'b1;
    assign sram_noe = 1'b1;
endmodule

Altera_Forum · ‎02-14-2012

After taking about a month off from working on the flash, I have repeated these steps with success. I initially had problems with the "Can't recognize silicon ID for device 1" errors which took several hours to work through. It ended up that if I set up the board to be programmed through the CPLD USB Blaster, everything worked perfectly. If I used my external USB Blaster device through the JTAG port, no matter what the switch and jumper settings were set to, I got the error after programming the FPGA and before any data was written to the flash. Odd!