Stuck at elaborating higher level entity

[Altera_Forum]

For some reason my projects stop compiling when the Analysis and Synthesis reach Elaborating Higher level entity. Even projects that had compiled perfectly in the past have failed to compile now because of this problem. 

 My professor and myself are stumped as to the cause of my dilema. if anyone can shed some light on this mystery I would appreciate any help.

[Altera_Forum]

Hi there, 

any message during compilation that pinpoints to some option being set or a failure detected?

[Altera_Forum]

Unfortunatly there is not, and there is only one indication that there is a problem at the Synthesis and Analysis level. 

 When it begins to compile it only compiles for 2 seconds on the Synthesis and Analysis Level. The overall timer continues but the timer next to the % complete is stuck at 2 seconds.

[Altera_Forum]

Did you try to delete the database and compile the project again? I had some cases with a database in a strange state that caused Quartus to freeze. Just delete the whole db folder in the project.

[Altera_Forum]

I have just tried your suggestion of deleting the database but there is still no change. Thank you for your idea though.

[Altera_Forum]

A possible explanation is an effectively non-synthesizable construct that doesn't immidiately reveal as such for Quartus. Testing the design with a simulator is one option, incrementally disabling parts of the design to narrow down the problem another one. 

 P.S.: Of course, there may be a Quartus bug, too.

[Altera_Forum]

are you trying to create a large ram? if it doesnt fit the quartus coding template for a ram it will try to build it out of registers and can take a looong time to compile it.

[Altera_Forum]

Thanks for your input guys but I'm starting to think that FvM's idea of a Quartus bug might be right. I've taken all of the suggestions thus far and considered them but the bug idea makes the most sense at this point. 

Any suggestions on how I might fix it if it is a bug?

[Altera_Forum]

report it to altera via mysupport. 

 Are you sure its not the ram template problem? can you post any code?

[Altera_Forum]

have you also tried a different version of quartus? (newest is 11.1)

[Altera_Forum]

Since the program is on the school's computer its at quartus 11.0. As for the code I've tried compileing a simple adder but it still will not compile and has the same problems with the other programs. 

 module adder(a,b,cin,s,cout);  parameter N = 8; input [N-1:0] a, b; input cin; output [N-1:0] s; output cout; assign {cout,s} = a + b + cin; endmodule

[Altera_Forum]

Did you solve this issue? 

I have the same problem here.  Quartus II 11.1 with a VHDL design. In every of my designs it hangs at the "elaborating...." between 9% and 18%.  Demo designs in Verilog can be compiled, but I don't see any setting changes compared to my project(s).

[Altera_Forum]

you could have something in your code that unrolls to a very large loop or generates a big bunch of logic that the Quartus synthesizer isn't able to process. It usually stops with an error, but I've seen it getting stuck in some cases too.

[Altera_Forum]

Indeed, yesterday night I discovered that too. 

Adjusted the code and now the problem is gone.  Thanks! :cool: