In my MAX10 project no synchronizer chains are recognized. As far as I understand a synchronizer chain begins with a asynchronous path to a register with is either:
-- altera vhdl_input_version vhdl_2008 library ieee; use ieee.std_logic_1164.all; entity bit_synchronizer is port( clk : in std_logic; -- clock async_i : in std_logic; -- async. input signal sync_o : out std_logic -- synchronized output signal ); end entity bit_synchronizer; architecture rtl of bit_synchronizer is signal meta : std_logic; signal sync : std_logic; attribute syn_preserve : boolean; attribute syn_keep: boolean; attribute syn_replicate : boolean; attribute syn_maxfan : integer; attribute syn_keep of meta : signal is true; attribute syn_keep of sync : signal is true; attribute syn_replicate of sync : signal is false; attribute syn_replicate of meta : signal is false; attribute syn_maxfan of meta : signal is 1; attribute altera_attribute : string; attribute altera_attribute of meta : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"; attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to """; begin process(clk) begin if(rising_edge(clk)) then meta <= async_i; sync <= meta; end if; end process; sync_o <= sync; end architecture rtl;I try to embed both the SDC constraints and assignments in the VHDL code to ease reuse. However, even when explicitly putting the same commands into the SDC and QSF file the synchronizer chain is not recognized. Neither the assignments nor constraints are listed as ignored in the reports. Any ideas?
I'm having same problem. I see there have been 563 views before mine and no answer has been provided?
You guys at Intel - common, fess up, is the set_false_path not supported in MAX10 family???