Synopsys Design Contraint

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Synopsys Design Contraint

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Hey guys,

I'm working with the DE2_70_TV program where you input a analog signal and output to the VGA. The sof file I program works fine but as soon as I compile the program, i have timing errors because the .sdc file is missing.

Where can I find this missing file? Ive read through the manuals and have tried constraining my output VGA signal to 60 hz to no avail.

Can anyone help?

To clarify, without the sdc file my video output is out of sync. I would like some pointers as to how to constrain a signal to VGA timing.

thanks

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