Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Synopsys SDC asyncronous clock

BTayl147
Beginner
271 Views

I have a design that uses memory mapped registers in an FPGA connected to a bus using an NXP processor.   The bus consists of a data bus, address bus, chip enable, and read and write lines.  I'm not sure how to constrain this ansycronous design.  The read and write signals are getting flagged as unconstrained clocks.  I believe that I need to constrain those as clocks and then setup input and output delays based on the read and write signals?   Would someone have an idea or an example as to the proper way to constrain a design like this?

 

I appreciate any help that someone might have!

Have a good day!

Brandon

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2 Replies
Nurina
Employee
150 Views

Hi, is it alright if you share your qar file? To generate a qar file, go to Project>Archive Project.


Thanks,

Nurina


Nurina
Employee
133 Views

Hi,


We did not receive any response to the previous reply provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,

Nurina


P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution.


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