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Valued Contributor III
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Synopsys VCS gets stuck

Hello, I am facing some weird problem with VCS. I am trying to simulate a simple RTL model with testbench in VCS. It's not possible include all the details of RTL model as its kinda big but in general what happens is, whenever I initialize the clk as '0' in testbench and run the simulation, it gets stuck. I have to force-stop it. I am generating the clock as bellow: 

 

always # 1 clk = ~clk; 

initial begin 

clk = 1; 

// delay and driving DUT inputs 

end 

 

I am not sure what is happening as I didn't face this problem before. I will appreciate any help in this matter. Thanks in advance.
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