Synplify Pro for resource optimization?

[Altera_Forum]

Hi there, 

 We have a design is approaching 90% full in a 3C25 device and the combinational logic resource is the bottleneck. Would Synplify Pro help in this case? If it does, how much difference would it be comparing to Quartus II with all area optimization options on? I understand different designs may have different results, but just want to get a feel.  Any comments would be appreciated.  Thanks, Hua

[Altera_Forum]

A few percent maybe, but I wouldn't expect something magic... I suppose it's even not worth trying when EP3C40 is almost pin-to-pin compatible to EP3C25...

[Altera_Forum]

No... our power budget is pretty tight.

[Altera_Forum]

Buying synplify would be cheaper? :)

[Altera_Forum]

I was talking about power budget... and yes, it would be cheaper if Synplify solves the problem

[Altera_Forum]

Well, I've given my opinion. You may want to hear someone else.

[Altera_Forum]

try contacting the local Synplify distributor and see if you can get an eval license

[Altera_Forum]

In the last year, I have not used Synplify much, but in prior years I have used it and compared the results to QIS on dozens of different designs. It is my experience that (and again, design dependent) Synplify Pro does a slightly better job of producing a smaller fit, but QIS usually gives you a design that meets timing a little easier.

[Altera_Forum]

My experience, with Altera, the tools usually do a pretty good job up to about 92-95% on the LE's. 

 I know Synplify use to do much better than Xilinx tools and was pretty much considered a requirement to a Xilinx flow. But since I been using Altera, I haven't seen a area where I would consider the cost worth it.  Quartus does a good job, and the Design Space Explorer usually gets you that few percentage more if you need it.  I would validate the size of the blocks make sense post synthesis. I've found cases in the past, where particular blocks were much larger than expected due to the way the source was written, and could be optimized by changing the RTL slightly.   Pete

[Altera_Forum]

it would probably be better if you tried to reduce the logic utilisation at the source code level rather than hoping the synthesis tool can squeeze a few percent for you.

[Altera_Forum]

If you read the reports about resources use of your design, isn't there a subsystem that uses a lot more than it should? In that case a rewrite of the source, as Tricky suggests, can have trumendous results. 

I recently had a design that took too many LEs for my taste, and I found a block that used 90% of the registers. That block was a VHDL array that stored some parameters. Reading the code in more details shown that what I described with the array was a triple port RAM instead of a dual port, as I thought I did. Rewriting the code to change it to a dual port made the synthesizer use an embedded RAM block instead of registers and the total number of LE was divided by 10. So sometimes little changes can lead to big improvements! Look especially for parts of the code that could use embedded blocks such as memories and multipliers, and check that the synthesizer indeed uses the embedded blocks instead of LEs. Some HDL code that look simple can also use a tremendous amount of registers in some cases, and rewriting it or using multiple clock cycles and share some resources between several blocks or functions can also give good results.