Synthesis of Verilog tasks in QuartusII - Intel Community

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Synthesis of Verilog tasks in QuartusII

1,858 Views

Are Verilog tasks synthesizable using the Quartus II synthesis tool?

Thanks in advance,

Johnnie.

Link Copied

2 Replies

1,157 Views

yes, here's a full list of support:

http://quartushelp.altera.com/current/mergedprojects/hdl/vlog/vlog_list_support.htm

Copy link

1,157 Views

Thank you v much

Copy link

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.