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Altera_Forum
Honored Contributor I
1,696 Views

SystemVerilog error: parameter with complex/aggregate value must have a type

Hi, everyone. I am the first time asking the questions here. 

I want to declare a double array parameter. 

However, I meet an error as below. 

Can someone help me?  

Thank you very much.  

 

error (10709): systemverilog error at command_lookup.v(87): parameter with complex/aggregate value must have a type 

parameter command = { // Clear the screen and set cursor position to home 8'h1B, // Esc 8'h5B, // [ 8'h6A, // j // Set the cursor position to row 0 column 3 8'h1B, // Esc 8'h5B, // [ 8'h30, // 0 8'h3B, // ; 8'h33, // 3 8'h48, // H // Text to print out on the screen 8'h48, // H 8'h65, // e 8'h6C, // l is lowercase L, not number one 8'h6C, // l is lowercase L, not number one 8'h6F, // o 8'h20, // Space 8'h46, // F 8'h72, // r 8'h6F, // o 8'h6D, // m // Set the cursor position to row 1 column 4 8'h1B, // Esc 8'h5B, // [ 8'h31, // 1 is number one not L 8'h3B, // ; 8'h34, // 4 8'h48, // H // Text to print out on the screen 8'h44, // D 8'h69, // i 8'h67, // g 8'h69, // i 8'h6C, // l is lowercase L, not number one 8'h65, // e 8'h6E, // n 8'h74, // t 8'h00 // Null };
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3 Replies
Altera_Forum
Honored Contributor I
356 Views

Change your declaration to  

 

parameter bit command = { // Clear the screen and set cursor position to home 

 

It is a good idea for any parameter declaration.
Altera_Forum
Honored Contributor I
356 Views

Thank you very much. I try it. 

However, I meet another error. 

 

Error (10161): Verilog HDL error at command_lookup.v(87): object "bit" is not declared. Verify the object name is correct. If the name is correct, declare the object. 

 

Do you know what it is?
Altera_Forum
Honored Contributor I
356 Views

have you saved the file with .sv extension? it is trying to compile it as verilog, not SV

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