I have a 12-bit serial 80MHZ lvds ADC from National clocked at 80MHZ coming in on two channels. One channel has a new sample every rising edge of the frame clock and the other on the falling. Therefore, the frame clock is coming in at 40MHz and the data clock is 240MHz. I understand the best approach for this is to pll the frame clock. However, I'm trying to get a better grasp of Time Quest and how it works. I've read Rysc's guide, which helps a lot. Unfortunately, in this situation I'm having trouble trying to get the correct timing constraints for the frame clock.
The data clock seems pretty simple just shift the clk coming in by 90 degrees and follow the example on Altera's site for center aligned source synchronous design. That seems to work just fine. Next, I set the false paths making sure there are no paths linking the rising edge of the data clk with the rising edge of the frame clk. This leaves me with the falling edge of the data clk and the rising edge of the frame clk giving me a setup time of 1.04ns. The hold time would then be the previous rising edge of the frame clock from the falling edge of the data clk or -23.96ns.
Here is the part I don't understand. Time Quest reports these relationships as .001ns for setup and .000ns for hold. Is there something I'm missing here?
