The clock output on the ALTLVDS_TX has a minimum divide ratio of 2. How can I make it 1?

[SreekumarR_G_Intel]

I am not sure which device you are targeting , Here is the screen shot example for Cyclone V. In IP megawizard you can change the core output clock to 1,2 , 4.

Hope helps,

Thank you,

Regards,

Sree

[GFros2]

Hi Sree,

Thanks for the reply. I think it is my fault. Everthing in the parameter settings above talks about the input and core clock. Nothing on the output clock. So I assumed te divide ratio was based on the input clock!

I am using Cyclone 10 parts with a serial link of seven bits per. So I need a divide by seven which was one of my options on the screen above.

Now runs fine.

Thanks,

Geoffrey