Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
I am not sure which device you are targeting , Here is the screen shot example for Cyclone V. In IP megawizard you can change the core output clock to 1,2 , 4.
Thanks for the reply. I think it is my fault. Everthing in the parameter settings above talks about the input and core clock. Nothing on the output clock. So I assumed te divide ratio was based on the input clock!
I am using Cyclone 10 parts with a serial link of seven bits per. So I need a divide by seven which was one of my options on the screen above.
