The quartus prime software quit unexpectedly(10M16SLY180)

[tiandada]

Unexpected software error when I use LVDS constraints for pinsUnexpected software error when I use LVDS constraints for pins.The error message is as follows.Device Information:10M16SLY180   , The LVDS output pin information is J5.

Problem Details
Error:
Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_manager_impl.cpp, Line: 18290
success
Stack Trace:
0x12db19: FIOMGR_IO_MANAGER_IMPL::get_tjnor + 0x389 (FITTER_FIOMGR)
0x12d63d: FIOMGR_IO_MANAGER_IMPL::get_tj_ssn_subtotal + 0x8d (FITTER_FIOMGR)
0x148556: FIOMGR_IO_MANAGER_IMPL::validate_lvds_tx + 0x7e6 (FITTER_FIOMGR)
0x11045c: FIOMGR_IO_MANAGER_IMPL::check_diff_io_physical_io_rules + 0xacc (FITTER_FIOMGR)
0x7d499: FIOMGR_IO::is_insertion_legal + 0xe59 (FITTER_FIOMGR)
0x133272: FIOMGR_IO_MANAGER_IMPL::is_insertion_legal_by_pad_id + 0xb2 (FITTER_FIOMGR)
0x9b18a: FIOMGR_IO_MANAGER::is_insertion_legal + 0x2ba (FITTER_FIOMGR)
0x98a2f: FIOMGR_IO_MANAGER::insert + 0xbf (FITTER_FIOMGR)
0x53760b: vpr_qi_place_io + 0xbb (fitter_vpr20kmain)
0x316e8c: l_aa_pl_positions_satisfy_io_constraints + 0x17c (fitter_vpr20kmain)
0x3143e4: l_aa_pl_move_is_legal + 0x1e4 (fitter_vpr20kmain)
0x3117fb: aa_pl_attempt_commit_move + 0x2b (fitter_vpr20kmain)
0x36d044: l_mpp_commit + 0x1b4 (fitter_vpr20kmain)
0x36f6eb: aa_mpp_perform_moves + 0x44b (fitter_vpr20kmain)
0x313410: l_aa_pl_perform_temperature + 0x220 (fitter_vpr20kmain)
0x3186bd: l_aa_pl_perform_anneal + 0xb9d (fitter_vpr20kmain)
0x311665: aa_pl_anneal + 0x95 (fitter_vpr20kmain)
0x307ea0: aa_pl_do_bulk_of_placement_phase + 0x650 (fitter_vpr20kmain)
0x307746: aa_try_place + 0x3a6 (fitter_vpr20kmain)
0x26ab11: aa_flow_do_placement_attempt + 0x21 (fitter_vpr20kmain)
0x26788b: aa_flow_place + 0x1db (fitter_vpr20kmain)
0x2673c4: aa_flow_fit + 0x64 (fitter_vpr20kmain)
0x55f8d8: VPR_QI_FACADE::vpr_qi_main + 0x68 (fitter_vpr20kmain)
0x38c84: fitapi_run_vpr + 0x84 (fitter_fitapi)
0x53158: FITCC_EXPERT::run_vpr + 0x138 (FITTER_FITCC)
0x52bed: FITCC_EXPERT::place_and_route + 0xfd (FITTER_FITCC)
0x51e3d: FITCC_EXPERT::invoke_fitter + 0x7bd (FITTER_FITCC)
0xb2c2: fcuda_execute + 0x1d2 (fitter_fcuda)
0xedbf: fmain_start + 0xa6f (FITTER_FMAIN)
0xb154: qfit_execute_fit + 0x454 (comp_qfit_legacy_flow)
0x1c4e: QFIT_FRAMEWORK::execute + 0x6fe (comp_qfit_legacy_flow)
0x19437: qfit_legacy_flow_run_legacy_fitter_flow + 0x2d7 (comp_qfit_legacy_flow)
0x14640: TclInvokeStringCommand + 0xf0 (tcl86)
0x16442: TclNRRunCallbacks + 0x62 (tcl86)
0x17c4d: TclEvalEx + 0x9ed (tcl86)
0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
0xa5136: Tcl_EvalFile + 0x36 (tcl86)
0x12435: qexe_evaluate_tcl_script + 0x4a5 (comp_qexe)
0x11393: qexe_do_tcl + 0x593 (comp_qexe)
0x176d6: qexe_run_tcl_option + 0x666 (comp_qexe)
0x37746: qcu_run_tcl_option + 0x1526 (comp_qcu)
0x16f1b: qexe_run + 0x39b (comp_qexe)
0x18012: qexe_standard_main + 0xb2 (comp_qexe)
0x1ea2: qfit2_main + 0x82 (quartus_fit)
0x12208: msg_main_thread + 0x18 (CCL_MSG)
0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG)
0x15f13: mem_thread_wrapper + 0x73 (ccl_mem)
0x11a41: msg_exe_main + 0xa1 (CCL_MSG)
0x29bf: __scrt_common_main_seh + 0x10b (quartus_fit)
0x1257c: BaseThreadInitThunk + 0x1c (KERNEL32)
0x5aa47: RtlUserThreadStart + 0x27 (ntdll)
End-trace
Executable: quartus
Comment:
None
System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Version: 23.1std.0
Build: 991
Edition: Standard Edition

[RichardTanSY_Intel]

I could not find this internal error in our database. Could you help to share your design .qar file (Project> Achieve Project) that could duplicate this error? This will requires the engineering team to investigate on this.

For all cases with Fatal errors or Internal errors, we need to obtain a design test case to duplicate the error. Without error duplication on our side, finding a workaround or solution becomes difficult.

p/s: please keep in mind that any work involving our engineering team may take some time, ranging from a few days to a few weeks, depending on the complexity of the issue.

Regards,

Richard Tan

[RichardTanSY_Intel]

Any update on this?

Do you able to share the design .qar?

Regards,

Richard Tan

[tiandada]

I've added the project where I submitted the question, but I don't see it here. Please check.

[RichardTanSY_Intel]

Are you referring to the tr.qar ? I believe I have see it attached in the system.

Regards,

Richard Tan

[tiandada]

Okay, if you can see it, there's no problem.

[RichardTanSY_Intel]

I able to duplicate the issue and have submitted a case to the engineering team to investigate. 

I will keep you updated as soon as there is any progress or findings.

p/s: Please keep in mind that any work involving our engineering team may take some time, ranging from a few days to a few weeks, depending on the complexity of the issue.

Regards,

Richard Tan

[RichardTanSY_Intel]

Just to inform you that the engineering team is still looking into this.

Regards,

Richard Tan

[RichardTanSY_Intel]

Hi,

Quick check with you, may I know the urgency for this issue? what is the impact ?

is it intended to set LVDS to LVDS_Tx node?

Regards,

Richard Tan

[tiandada]

We need to make a prototype in May.I need LVDS_TX and I need LVDS_RX.

[RichardTanSY_Intel]

Do you have a specific date when you need this issue to be fixed? 
Thanks. 

Regards,

Richard Tan

[RichardTanSY_Intel]

The engineering might take some time to investigate this as it is old devices.

Is it possible to change the device to 10M16SAU169I7G? As this device able to pass the fitter.

FYI, the device is SA as compared to SL.

SA : Single supply - analog and flash features with RSU option

SL : Single supply - flash features with RSU option

https://www.intel.com/content/www/us/en/docs/programmable/683658/current/device-ordering-information.html

Regards,

Richard Tan

[tiandada]

The circuit board has been made, And the chip is already assembled. In addition, the size of the 10M16SAU169I7G  is also too large.

I would like to have this problem solved by May 10, if possible. Thank you!

[tiandada]

Is there any update? thanks

[RichardTanSY_Intel]

Sorry for the delay, I was on leave last week. I will check with the engineering team for possible solution.

Regards,

Richard Tan

[tiandada]

Hello, do you have the solution?

[RichardTanSY_Intel]

I'm still consulting with the engineering team to find a solution. It appears that the person who handled the code left the company a long time ago, which has caused some delay.

Apologies for any inconvenience this may have caused.

Regards,

Richard Tan

[RichardTanSY_Intel]

Hi,

Could you help to provide the full design ? The previous design provided seems to be simplified design.

We would like to understand how the LVDS is assigned in the bank.

Is there any single-ended IO assigned together with the LVDS in the same IO bank?

Alternatively, you can provide the pin planner details of the full design.

With this information, engineering could speed up the fix. Otherwise, the fix is estimated to take a month.

Let me know if you prefer the file transfer through secure FTP. (File transfer protocol).

Regards,

Richard Tan