Timing Violations after upgrading to Quartus Pro

[anonimcs]

Hi all,

I have a project working perfectly on Quartus Prime Standard version 17.1, which doesn't have any timing errors. Due to an interest of using higher speed bins for the external DDR memory (EMIF IP in Standard Quartus supports up to -2666 but Pro version supports -3200 MT/s), I wanted to upgrade the Quartus version I'm using for my project to Quartus Pro version 21.3.

Even though I haven't changed anything in the Platform designer (I haven't even implemented the DDR change I mentioned above), I'm getting multiple timing violations on Quartus Pro. I have failing Setup/Hold/Removal timings where the VHDL hasn't changed for a bit (considering the code for my IPs, not the generated glue logic etc by Intel). I have a feeling that the integration to the Pro version hasn't been successful, these timing errors wouldn't make any sense to me otherwise. Do you guys know what the issue here might be ? 

[sstrell]

I'm presuming this is Arria 10 because that's the only device family supported in both Standard and Pro.  Have you upgraded/regenerated the EMIF IP (and others)?  That's pretty much required when you move to a new version of the software or especially moving from Standard to Pro.

Where are the timing issues located?

[anonimcs]

Yes, the target FPGA is indeed an Arria 10. I have upgraded and regenerated all the IPs in the design, including the EMIF IP. The version 19.1 is used for EMIF IP.

And the location of the issues are listed below:

- Removal violation: PLL output clk

- Hold violation: PLL output clk (another PLL instance, not the same as Removal violation)

- Setup violations: PLL output clk (same PLL as Hold violation), EMIF DDR4 Core usr clk, and some other clk outs from some instantiated modules which take a reference clock directly from FPGA pins

[sstrell]

This doesn't really help.  Can you show timing reports?  Did you run Report DDR in the timing analyzer?  Are the timing failures specifically with the EMIF or are they related to any other parts of your design?  What does your top-level .sdc file look like?

[anonimcs]

I figured the root cause, and for that I created an entry of its own, which can be found in the community with the title "Clock groups ignored by Timing analyzer". There I shared the report and the related parts of my .sdc file

[RichardTanSY_Intel]

Since a new thread/forum case has been filed to further discuss the root cause, can I consider this thread closed?

Link: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Clock-groups-ignored-by-Timing-analyzer/m-p/1597615

Regards,

Richard Tan

[anonimcs]

Sure

[RichardTanSY_Intel]

Thank you for the confirmation.

I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan