FPGA:1SG280LU2F50E2LG Quartus II 20.1
VCCH_GXB, VCCR_GXB and VCCT_GXB are connected to GND
Pin Planner，TBE0n->AF16(any Pin in the 3.0v Bank 6A, 6C, 7A or 7C)，I/O Standard is selected 3.0-V LVCOMS(or 3.0-V LVTTL )
The project is compiled successfully
When downloading the sof file to 9%, the following error occurs
Device has stopped receiving configuration data
Error message received from device: Detected internal error. Contact Intel Applications for further assistance. (subcode 0x002D, Info 0x00000000, Location 0x0010800)
Operation failed Pin Planner，
TBE0n->XX(the pin is not in the in the 3.0v Bank 6A, 6C, 7A or 7C)，I/O Standard is selected 1.8v. The project is compiled successfully and the the sof file is downloaded successfully.
The error may come up due to a PLL calibration failure of the input reference clocks resulting in failure at about 23% during the programming stage.
Please refer to this link: https://www.intel.com/content/www/us/en/support/programmable/articles/000075102.html
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