What is the motivation behind the creation of Data Pattern Generator/Checker Verification IP?

[okhajut]

The Intel Quartus Prime Platform Designer contains some verification IP that contains the terms "Pattern Checker" and "Pattern Generator" in their name. These were added quite late into the IP suite provided with Quartus Prime.

The Quartus Prime already has had Avalon MM master/slave, Avalon ST source/sink BFM IPs for many years. What then is the motivation behind creation of these new pattern generator and checker verification IP? Can't the same task be performed using the existing BFMs anyway?

I am asking this question because the motivation behind creation of these verification IP and why one should need them is not clear.

[sstrell]

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/functional-description-99396.html

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/functional-description-98366.html

For synthesis vs. the BFMs, which are only for simulation.

[Kenny_Tan]

Sstrel is right, this IP usually is use for simulation purposes.

You may take a look the user guide https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/data-pattern-generator-and-checker.html

And we also have design example here:

https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-ALTLVDS-Design-Example/ta-p/735385

[Kenny_Tan]

Hi,

Not sure if you have further question on this? If no, we shall close this thread.

Thanks,

[Kenny_Tan]

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