i am working on a project with Stratix 10 Device.
i have tried to implement System Verilog Rom (not as IP) in my design.
the problem is that some ROM's Quartus translate correctly as a RAM and some Not (i saw Register implementation).
my Syn flow it's like that:
Compile & Mapping - Synplify Premier 21.9
Place & Route - Quartus 21.2
can you please look at the code below and understand what is the issue?
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The keypoint is that block RAM hardware in all Intel FPGA families uses registered addresses. Read data can be optionally registered. Therefore HDL code that shall successfully infer block RAM must register address.
If you look at simple ROM HDL templates, the address register must not necessarily appear as such. If you register the ROM output, e.g. as in your code but without the read enable (cs) function, synthesis converts the data register into an address register.
The cs function in your code however blocks this possibility. You would need a second output register to make your code synthesizable in block RAM. That's due to properties of the FPGA hardware and has nothing to do with tool, e.g. Synplify limitations. Quartus software manual explains the requirements for RAM/ROM inference in detail, just study.