Rom implementation on Quartus

[Niv_Amsalem]

Hi All,

i am working on a project with Stratix 10 Device.

i have tried to implement System Verilog Rom (not as IP) in my design.

the problem is that some ROM's Quartus translate correctly as a RAM and some Not (i saw Register implementation).

my Syn flow it's like that:

Compile & Mapping - Synplify Premier 21.9

Place & Route - Quartus  21.2

can you please look at the code below and understand what is the issue?

Thanks

Niv.

[sstrell]

Looking at a template in the text editor, there is no CS signal used.  Also, why are you using a generate statement and a genvar that you are not using anywhere?

[SyafieqS]

Hi,

Have you tried to use any Quartus template for the ROM?

You may take a look a the template ROM insert template --> sv--> full design --> ram/rom

[SyafieqS]

May I know if there is any update from previous reply? 

As the snippet you posted is different from the Quartus template

[Niv_Amsalem]

Hi,

i suspect that the Synplify Premier in the Mapping stage determine if it's implemented as Registers or not.

so it's under investigation.

i will update once i will have an answer.

Thanks

Niv.

[SyafieqS]

Hello Niv,

Understood. Let me know if there is any other concern or update on this.

[SyafieqS]

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[Niv_Amsalem]

Hi,

i have a question.

when i open Quartus IP of ROM i see that the address must be registered, why is that?

is that a mandatory demand for ROM?

Thanks

Niv.

[hashkellfieldblocks]

Possibly need at ROM
https://chat.openai.com/share/e0721c7f-42e3-43c9-9b4b-1d8d3d5316e4

[FvM]

The keypoint is that block RAM hardware in all Intel FPGA families uses registered addresses. Read data can be optionally registered. Therefore HDL code that shall successfully infer block RAM must register address.

If you look at simple ROM HDL templates, the address register must not necessarily appear as such. If you register the ROM output, e.g. as in your code but without the read enable (cs) function, synthesis converts the data register into an address register.

The cs function in your code however blocks this possibility. You would need a second output register to make your code synthesizable in block RAM. That's due to properties of the FPGA hardware and has nothing to do with tool, e.g. Synplify limitations. Quartus software manual explains the requirements for RAM/ROM inference in detail, just study.

[hashkellfieldblocks]

The input port mem clk should be input, not input mem.
The always block should use non-blocking assignment (<=) to assign values to mem_rd.
Here's the corrected module declaration:

verilog
Copy code
module rom_lp_M20K #(
parameter MEM_INIT = "", // Memory initialization file
parameter int unsigned MEM_DEPTH = 4,
parameter int unsigned ADDR_WIDTH = 2,
parameter int unsigned DATA_WIDTH = 64
)(
input clk,
input [ADDR_WIDTH-1:0] mem_addr,
input mem_cs,
output reg [DATA_WIDTH-1:0] mem_rd
);
And here's the corrected always block:

verilog
Copy code


always @ (posedge clk) begin
if (mem_cs) begin
mem_rd <= mem[mem_addr];
end
end

Greetings, if you dont mind would you follow up post research that have been at ChatGpt and contact at email codeblochness@gmail.com

https://chatgpt.com/share/a345ecbb-203f-4d63-8f9f-0cfeb86d098f?oai-dm=1

Thank you

[FvM]

Hi,
if this is and the previous late thread response are ChatGPT experiments, they clearly failed. 

They miss to analyse the problem of the original post. The latest code is exactly reproducing the original problem and can't infer ROM, due to cs usage, as explained above.

The verbose ChatGPT answer  "Register Address for QuartusROM" quoted above is at least partly misleading and doesn't help to solve the discussed problem. The key point is to understand what is required to infer memory from HDL code. Your code can be only mapped to FPGA hardware if it corresponds to the block RAM topology, need to understand which signals are unconditionally and which optionally registered. 

I appreciate that you are not directly spamming the thread with ChatGPT answers.

Regards

Frank