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Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17049 Discussions

The signal does not hold its value outside clock edge

Altera_Forum
Honored Contributor II
2,718 Views

Please help me with an error in my code. 

I need that when a button is pressed, the signal changes its value. But the quartus says he can not infer a register for it. 

I found a resolution, which is here:http://quartushelp.altera.com/14.0/mergedprojects/msgs/msgs/evrfx_vhdl_is_not_synthesizable_since_it_does_not_hold_its_value.htm

But I do not know the reset utility there. Only need the button. 

Thank you. 

 

Code: 

 

accept_seconds: PROCESS(enable,data) --processo de aceitar ou não os segundos inseridos. BEGIN -- IF(enable='0') THEN IF(FALLING_EDGE(enable)) THEN IF(data>="000000" AND data<="111011") THEN tempoutput <= '1'; tempsave <= '1'; ELSE tempoutput <= '0'; tempsave <= '0'; END IF; -- END IF; ELSE tempsave <= '0'; END IF;
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Altera_Forum
Honored Contributor II
1,592 Views

Put the enable inside the clock...

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Altera_Forum
Honored Contributor II
1,592 Views

how? I didn't understand.

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Altera_Forum
Honored Contributor II
1,592 Views

Currently toy have an asynchronous enable. Make it synchronous by making the clock the outer most thing in the process.

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Altera_Forum
Honored Contributor II
1,592 Views

I see that there are two lines commented out, these change the functionality of the code enormously as the END IF is for the second for loop. Was this something you did to try and get it working?

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