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hello everybody, (sorry if I do not write well in english but i'm a poor student...)
I have some problem with the use of the shift operators.. The goal of the program is realized an iir filter of order 2. I want shift right an integer ( acc) but the altera compiler will not let me .. it gets angry! why? it generate error: error (10327): VHDL error at filter_iir.vhd(81): can't determine definition of operator ""sll"" -- found 0 possible definitions So i think that there is a problem about library i include a lot of library but the compiler it's always angry! why? :confused: i enclose my code here: --file1 PACKAGE n_bit_int IS SUBTYPE BITS11 IS INTEGER RANGE 0 TO 1023; -- 11 bit SUBTYPE BITS22 IS INTEGER RANGE 0 TO 2097151; -- 22 bit SUBTYPE BITS15 IS INTEGER RANGE 0 TO 32768; -- 15 bit SUBTYPE BITS14 IS INTEGER RANGE 0 TO 16384; -- 14 bit TYPE ARRAY_BITS15 IS ARRAY(NATURAL RANGE <>) OF BITS15; TYPE ARRAY_BITS11 IS ARRAY(NATURAL RANGE <>) OF BITS11; TYPE ARRAY_BITS22 IS ARRAY(NATURAL RANGE <>) OF BITS22; TYPE ARRAY_BITS14 IS ARRAY(NATURAL RANGE <>) OF BITS14; END n_bit_int; --file2 LIBRARY work; USE work.n_bit_int.ALL; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; use ieee.numeric_std.all; use ieee.std_logic_signed.all; ENTITY filter_iir IS GENERIC ( L: INTEGER :=3; -- order filter L-1 W1: INTEGER :=11; W2: INTEGER :=22; W3: INTEGER :=15; W4: INTEGER :=14 ); PORT ( x_in :IN BITS11; --INPUT y_out :OUT BITS14; --RESULT debugx :OUT BITS22; debugx1 :OUT BITS22; debugx2 :OUT BITS22; debugx3 :OUT BITS22; debugy0 :OUT BITS15; debugy1 :OUT BITS15; debugy2 :OUT BITS15; clk : IN STD_LOGIC); END filter_iir; ARCHITECTURE myiir of FILTER_IIR IS SIGNAL x : ARRAY_BITS11 (0 TO L-1); SIGNAL x_num : ARRAY_BITS22 (0 TO L-1); SIGNAL i,j : integer :=0; shared variable y_den: ARRAY_BITS22(0 TO L-2); shared variable y : ARRAY_BITS15(0 TO L-2); shared variable acc : integer; BEGIN PROCESS BEGIN WAIT UNTIL clk='1'; -- esempio butterworth ordine 2 x(0)<=x_in; x_num(0)<=281*x(0); -- b0x(k) debugx<=x_num(0); x_num(1)<=562*x(1); -- b1x(k-1) debugx1<=x_num(1); x_num(2)<=281*x(2); -- b2x(k-2) debugx2<=x_num(2); for i in 0 to L-2 loop x(i+1)<=x(i); end loop; for j in 0 to L-3 loop y(j+1):=y(j); end loop; y(0):=(x_num(0)+x_num(1)+x_num(2)+y_den(0)+y_den(1)); debugy0<=y(0); acc:=y(0); y(0):= acc sll 10; y_den(0):=-75*y(0); -- a1y(k-1) debugy1<=y_den(0); y_den(1):=176*y(1); -- a2y(k-2) debugy2<=y_den(1); end process; y_out<=y(0); end myiir; Somebody can you help me? thank you!:rolleyes: good Easter! EnricoLink Copied
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In numeric_std, sll is defined for signed and unsigned.
So you need to convert your integer to unsigned, then convert the result back to integer y(0) := to_integer( to_unsigned(acc, 16) sll 10 );- Mark as New
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And pre-empting the next post about it still not working, you need to delete std_logic_arith from the libraries (you shouldnt be using it anyway as it's non-standard).
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