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Altera_Forum
Honored Contributor I
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TimeQuest / DE1-SoC Design Contraint File

Hi, 

I've downloaded the SDC file from the university program page (https://university.altera.com/redirect/materials?id=/pub/intel_material/boards/de1-soc/de1_soc.sdc). 

This file contains some entries about the external SDRAM Chip, like this regarding the clock. 

create_clock -period "100 MHz" -name clk_dram  

Now I use this SDRAM PLL from the university program library (System and SDRAM Clocks for DE series boards) to generate a clock of 143MHz and the SDRAM Controller IP. 

The SDRAM Clock (with a phase shift of -153°) is connected to the DRAM_CLK output port and the SYSTEM Clock is connected to the SDRAM Controller. Using this setup, I've  

removed the line above from the SDC file and added these three lines instead: 

create_generated_clock -source {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~FRACTIONAL_PLL|refclkin} -divide_by 10 -multiply_by 143 -duty_cycle 50.00 -name SDRAM_PLL_FRACTIONAL {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} create_generated_clock -source {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 5 -duty_cycle 50.00 -name clk_dram {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} create_generated_clock -source {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 5 -phase -153.00 -duty_cycle 50.00 -name clk_dram_chip {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}  

The SDC file also contains some output / input delay constraints like (for all output / input ports) 

set_output_delay -max -clock clk_dram 1.452 set_output_delay -min -clock clk_dram -0.857 set_output_delay -max -clock clk_dram 1.531 set_output_delay -min -clock clk_dram -0.805  

 

 

Now when synthesize my design, I get a couple of "timing requirements not met" warnings like shown in the attached thumbnail. I don't think that those paths are in my responsibility (direct connections from IP to SDRAM port). 

So my questions are: 

1) Do I have to change the set_output_delay values because of the changed clock? If yes, where can I find the correct values. 

2) Is there any issue caused by replacing the "create_clock" line with the three lines I posted above? 

 

 

PS: A high resolution version of the image can be found here: http://imgur.com/a/aov0g 

 

 

Thank you in advance, 

Martin
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2 Replies
Altera_Forum
Honored Contributor I
28 Views

Hmm, what happened to my topic above - there's just nothing?

Altera_Forum
Honored Contributor I
28 Views

Can be deleted - I've created a now topic.

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