Hi guys,
I have a problem with closing timing on design in just inherited.
I need to define the clock relationship between a clock that is generated in the fpga and then goes out to another device, through it and then back into the fpga where it is used to clock logic.
The base clock is 66Mhz that is multiplied up with a PLL to a 308Mhz (14/3). it then goes out to a external device on a LVDS interface. The external device then feeds the clock back into the fpga with some data. I have a LVDS receiver that receives the clock and devides it down by 10 so I have 61,6Mhz clock. There are data signals (configuration) comming from the 66Mhz domain to 61,6Mhz and then some status signals going back.
How can I define this external clock path in TimeQuest and the clock relationships?
I'm also having problems with recovery/removal on this related to resets and clear signal on FIFOS where the data is crossing back to the 66Mhz domain....
All help greatly appreciated and if you have some hints to examples its superb.
Cheers
Stefan
