TimeQuest Question

[Altera_Forum]

Hi, 

I am a newby using timequest and I have a question. In my project there is a master clock of 30 MHz and I have a filter working at a freqeuency = master clock / 4. Should I write a multicycle command in sdc file for all path inside the filter or there is a faster way to tell timequest that the filter is working at a lower frequency?   Thanks

[Altera_Forum]

Firstly, 30MHz is too low anyway and you may not need any extra constraints. 

 Secondly, if you do want multicycle then apply it to the registers fed by clock enable signal that determines filter speed.  Thirdly, as a side note. If you have so much speed why not use it for time folding your filter if you need to share resource.

[Altera_Forum]

Depends. 

a) If your filter is running on a divided clock generated by a PLL, you can just add a "derive_ppl_clocks" command to the .sdc. You could also manually use a "create_generated_clock" constrain though.  b) If your filter is running on a 1/4 clock enable, the multicycle path is the correct aproach.  c) If your filter is running on a divided clock generated by logic. you need a "create_generated_clock" command. "b" would be a better option though.

[Altera_Forum]

My project is based on a cyclone II anche the filter is narrowband band pass with 16 input ant 60 taps. I had warning n the same place using quartus v 9 and the classic timing analyzer, so I suppose the clock settings are right. 

The clock is divided using the clock enable approach so reading the documentation of timeqest the multicycle semms to be the right way... Anyway there are more than 100 setup warning so my question rised to understand if there is a faster way to introduce multicycle settings bacause the project is in the eary stage and I am not sure the fulter I ma usung will be the definitive one.  Kaz I suppose all the registers in the filter are fed by the clock enable but the multicycle setting can be applied only to path or I am wrong?

[Altera_Forum]

Yes you apply multicycle to clock enable. See altera example on clock enable multicycle constraint(Timequest resource centre). 

 If your filter is 60 taps, I will rather run it at max speed as this reduces resource by 1/4.   If you are having timing violations at such low speed then see if your clocking is safe

[Altera_Forum]

Thanks to all guys... to make all multiclicle assignement faster I found ot is possible to set the assigment to the "net" without usign "from" and "to". 

 Bye :)