TimeQuest/SDC - How Do I Specify Constraints Relative to Output Clock

[Altera_Forum]

Hi 

 I am just learning to use Quartus and TimeQuest, and am trying to figure out if it's possible to define a timing constraint relative to an output clock.   I have data (d) clocked out by a DDIO register driven by clock clk, and an output clock (k) generated by another DDIO register, clocked by clk90 (clk delayed by 90 degrees). Note the phase information may not be relevant to my question.   Basically, I am driving a peripheral which has setup and hold requirements for d relative to k. How can I specify these setup and hold specs as constraints for the FPGA? One tricky issue is that d is not clocked by k.   Thanks, Chris

[Altera_Forum]

Chris, 

 Rysc wrote a brillant document on this exact issue.    If you google    "how to constraint source-synchronous double-data rate interfaces"   You will find it as a hit in the altera forum.   I am doing this same thing and posted a question a day ago about "extra timing paths in DDR". If you look at that my .sdc is attached   C

[Altera_Forum]

--- Quote Start ---  Chris,   Rysc wrote a brillant document on this exact issue.   "how to constraint source-synchronous double-data rate interfaces"  You will find it as a hit in the altera forum.  I am doing this same thing and posted a question a day ago about "extra timing paths in DDR". If you look at that my .sdc is attached  C  --- Quote End ---    Good summary.  However there is simpler way that cover majority of non-DRAM source-synchronous DDR and SDR transmission cases. The solution is based on fact that in Quartus II 9.1 set_max_skew command finally works as expected*.  The most common case of source-synchronous interface is the case in which transmitter is expected to drive the data signals as closely as possible to the clock/strobe signals. In this case, assuming that you already defined characteristics the internal clock, all you need is a single set_max_skew command.  Example: RGMII Tx interface to the Ethernet Phy (MARVELL 88E1118 in "add delay" timing mode). The phy expects stable data signals within [0.9..2.7] ns window from tx clock edge. It means that, assuming the skew on PCB, the change of data should happen in [-1.3..+0.9] ns window from the clock edge. Let's say, the PCB eats +/- 0.3ns from the skew margin.  It means that if you request max skew < 0.6ns you should be on the safe side. So just the following line to your sdc: set_max_skew -to {tx_clk txd [*] tx_ctrl[0]} 0.6  Sure, the requirements established by this line are slightly stricter than what's absolutely needed, but it's simple and it works.  --- * - Please don't wast your time trying it with earlier versions of Quartus.

[Altera_Forum]

Thanks, all. Great information. 

 Chris