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Hi guys,
I was wondering if someone could help me understand why Tcl command 'set' and its respective variable (dereferenced with $) are not recognized by set_clock_groups SDC command? For instance, I have a PLL generated clock: inst19|altpll_component|auto_generated|pll1|clk[0] And I want to cut its name down, so it would be easier to use it later, so I write: set clk_40 inst19|altpll_component|auto_generated|pll1|clk[0] Now, I can reference the signal by writing $clk_40, but this is not working for the set_clock_groups command: set_clock_groups -asynchronous -group {clk_24 $clk_40} Btw, clk_24 is the clock name of the PLL inclk, and it gets recognized (of course), but $clk_40 doesn't. Also, even stranger thing is that set_false_path command seems to properly see $clk_40. (?!?) Anyone got any idea? I'm using Quartus 10.1 sp1.Link Copied
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Try this:
set clk_40 inst19|altpll_component|auto_generated|pll1|clk
set_clock_groups -asynchronous -group list $clk_40 clk_24]
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The curly brackets mean to take the contents literally, so:
{$clk_40} will search for a clock that matches $clk_40, not what you have set it to. Use quotes for a list with substititution: "$clk_40 clk_24" Escape anything that might cause problems: "$clk_40 altpll|pll|clk\[1\]" AndrewS6's advice should work too. One other thing I've seen is that set_clock_groups must be to the clock name, not the physical node in the design. So double-click on Report Clocks and make sure you're matching a name in the first column, not the last.- Mark as New
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Thanks guys, double quotes did the trick. I think I've spent a full day trying to make it work.
Btw, I've read almost all of your TimeQuest manual Rysc, pretty awesome work. Still, there is a few things I'm missing (mostly regarding some multicycle assignments, since I have a regular clock for Altera's TSE and 90 deg phase shifted for TX clock of the GMII i/f of the PHY - data is arriving way too late; everyone on the forum seem to have RGMII PHY and I can't get all the answers I need), so don't mind if I start a new thread regarding that :). I just want to make sure all the clock assignments are correct first.
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