[TimeQuest] constrain path between clock domain

[Altera_Forum]

Hello, 

 I'm having a FPGA Project, with multiple clock domains. The clocks are asynchronous, so i used "set_clock_groups -asynchronous". Every path between those clocks are now false path, but there are a lot of path between them. It doesn't matter how long the delay between them is, but i want those path to be from equal delay. (Sorry for my bad english).  For example, I have 4 Registers from time domain A feeding a register on domain B(through a multiplexer) . All path are false path. I report false path to check timing, one register has -2 ns slack(less then 1 period) others has -11 ns (more than 3 clock cycle), clock relationship 1 ps, because clocks are unrelated. I want all register to register delay to be equal.   How can i constrain those path delay? Is set_clock_group -asynchronous correct?  I can't use a FIFO on every Path between those clock domain.  Thank you.

[Altera_Forum]

--- Quote Start ---  Hello,   I'm having a FPGA Project, with multiple clock domains. The clocks are asynchronous, so i used "set_clock_groups -asynchronous". Every path between those clocks are now false path, but there are a lot of path between them. It doesn't matter how long the delay between them is, but i want those path to be from equal delay. (Sorry for my bad english).  For example, I have 4 Registers from time domain A feeding a register on domain B(through a multiplexer) . All path are false path. I report false path to check timing, one register has -2 ns slack(less then 1 period) others has -11 ns (more than 3 clock cycle), clock relationship 1 ps, because clocks are unrelated. I want all register to register delay to be equal.    How can i constrain those path delay? Is set_clock_group -asynchronous correct?    --- Quote End ---     You can't reliably do anything in an FPGA about controlling delays therefore you can't do anything to make any delays (even just two) equal.     --- Quote Start ---  I can't use a FIFO on every Path between those clock domain.  --- Quote End ---     Then you'll need to seriously rethink your FPGA design. You have two choices when crossing clock domains: - FIFO - Synchronizing a control/status signal to indicate when data is being transmitted across the clock boundary.   Kevin Jennings

[Altera_Forum]

What do you mean by equal? Within 100ps of each other? 10ns? When I've been asked similar questions, the user just means they don't want them too far from each other, but don't really know what that is. Try to think of what a failure looks like, i.e. if one is 10ns and another path is 3ns, how would that actually fail in hardware? Becuase they're asynchronous, they could be off by a whole clock cycle. 

And remember that being asynchronous transfers, the latching register could always go metastable. Are you handling that too? Most systems try to limit transfers between domains to a core point, transfer everything over with a FIFO, and then continue in the other domain. It may be a wide data path and lots of control signals, but it's all done with the same FIFO. Finally, I would recommend a skew constraint. I have seen some users not use set_clock_groups and instead do something like: set_max_delay -from [get_clocks A] -to [get_clocks B] 10.0 set_min_delay -from [get_clocks A] -to [get_clocks B] -5.0 This does include clock skew in the calculation(which I would argue is correct), but gives a range. I'm not a huge fan of it, but get it.

[Altera_Forum]

Thanks for your reply. 

 J_k you're right, in a new design it is changed. In the existing, this is not possible.  Rysc: In most transitions a FIFO or Data_valid signal is used. For these transitions synchronization chains are used to avoid metastability problems.  An exact equal delay is not necessary. And I know that this can not be achieved. My problem is that, without limitation, the times between different translations are very different. The receiver clock is higher than the transmitter clock. Therefore, the difference can be greater than one receiver clock cycle, but must be less than 2 clock cycles. In some translation it is more than 3 cycles delay.   I will use set_min / max delay and skew assignment trying to minimize this difference. All other paths between the clock domain should be set individually as false path?