TimeQuest relative time specification

[Altera_Forum]

Hi 

 I need some timing constraints for an ARM trace port. It consists of four data output lines and a clock output. In the best case, the data lines change in the middle of two clock flanks (both flanks are used).  All those five signals (including "clock") are driven by a register going directly to the pin, no additional logic inbetween. They have the same driving clock.  To have this shift between the clock flanks and the data changes, I tried to specify a different delay for clock and data. But so far I can only do that in an absolute manner, related to a driving clock or similar. What I would prefer is a statement, that says: "Clock is 10ns later than data" without considering the clock network.  Any idea how to do that? Any idea if the Quartus fitter manages to build such a delay? The pin output delay lines are too small for this...  Hope I made myself clear enough ;) Thanks in advance for all input emanuel

[Altera_Forum]

--- Quote Start ---  Hi  I need some timing constraints for an ARM trace port. It consists of four data output lines and a clock output. In the best case, the data lines change in the middle of two clock flanks (both flanks are used).  All those five signals (including "clock") are driven by a register going directly to the pin, no additional logic inbetween. They have the same driving clock.  To have this shift between the clock flanks and the data changes, I tried to specify a different delay for clock and data. But so far I can only do that in an absolute manner, related to a driving clock or similar. What I would prefer is a statement, that says: "Clock is 10ns later than data" without considering the clock network.  Any idea how to do that? Any idea if the Quartus fitter manages to build such a delay? The pin output delay lines are too small for this...  Hope I made myself clear enough ;) Thanks in advance for all input emanuel  --- Quote End ---     Hi,  are you talking about a source-synchronous output ?  Kind regards  GPK

[Altera_Forum]

Hi 

 You could call it source synchronous. Problem is: the "clock output" looks like just another data signal for the timing analysis.  there are five registers, all clocked by one clock with 50MHz. four of them just register data and directly feed a pin. the last one has output feeding a pin and connected to the input through an inverter, i.e. cuts the clock in half.  on the outside, this looks like a data bus with data transfer on both flanks. but yes, source synchronous. inside the fpga i just have five signals.  what I didn't try is to specify a clock on that fifth signal... but how to specify a clock that is active on both flanks? just double the speed?  thanks and best regards, emanuel

[Altera_Forum]

--- Quote Start ---  Hi  You could call it source synchronous. Problem is: the "clock output" looks like just another data signal for the timing analysis.  there are five registers, all clocked by one clock with 50MHz. four of them just register data and directly feed a pin. the last one has output feeding a pin and connected to the input through an inverter, i.e. cuts the clock in half.  on the outside, this looks like a data bus with data transfer on both flanks. but yes, source synchronous. inside the fpga i just have five signals.  what I didn't try is to specify a clock on that fifth signal... but how to specify a clock that is active on both flanks? just double the speed?  thanks and best regards, emanuel  --- Quote End ---    Hi Emanuel,  have a look to this application note:  http://www.altera.com/literature/an/an433.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=an433&gsa_pos=1&wt.oss_r=1&wt.oss=an433  Maybe it will answer your questions.  Kind regards  GPK

[Altera_Forum]

Hi GPK 

 thanks a lot for the pointer! I haven't seen this application note so far - but there's more than one thing I can use it for ;)  I'll study that and see if I get the right constraints together.  Thanks a lot and best regards, emanuel