Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Timequest GUI

Altera_Forum
Honored Contributor II
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Hi, 

my question considers the TimeQuest time analysis. Can someone explain me why does the Data Arrival/Required waveline changes after the latch clock ? From what I know it shall change before Latch time and stay stable during Tsetup time... 

 

 

best regards 

Joel
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Altera_Forum
Honored Contributor II
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From your latch clock, there is a clock delay, pessimisim, uncertainty, etc. that changes when the actual latch clock hits the latching register. That being said, the data does arrive after this, and the slack is negative. So you're right, this is incorrect and it's basically telling you that this path failed timing. It should be in red, and negative slacks mean they failed timing.

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Altera_Forum
Honored Contributor II
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I understand it now. What I missed was the bottom Clock Delay which is shown in respect to the Latch Clock. And the Clock Delay on the top is shown in respect to the Launch Clock. Its all clear now. Thank you.

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