I read some documentation about the source synchronous interface (Rysc one, AN433, altera web site etc...) but it's still a bit confusing for me.
So, my Stratix V is interfaced with a ADC AD9230 wich provides SDR edge aligned 12 bits parallel data '"adc_d_ext" and a 200 MHz clock signal "adc_dco_ext".
The ADC datasheet indicates a skew between the data and clock of -0.3 ns min and +0.5 ns max.
I followed litterature recommendations so I use a fPLL in source synchronous mode sourced by adc_dco_ext to generate a 180° shifted clock to latch the data bus inside the FPGA.
The sdc constraints are :
----------------------------------------
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
create_clock -period 5 -name adc_dco_ext [get_ports {adc_dco_ext}] -- creation of the FPGA input clock (source of the PLL)
create_clock -period 5 -name virt_adc_dco_ext -- creation of the ADC virtual clock
set_input_delay -add_delay -clock virt_adc_dco_ext -max 0.5 [get_ports {adc_d_ext[*]}]
set_input_delay -add_delay -clock virt_adc_dco_ext -min -0.3 [get_ports {adc_d_ext[*]}]
----------------------------------------
Do you think they are correct ?
Thank you very much for your support.
