Timequest: Source synchronous timing isn't moving when I adjust PLL

[Altera_Forum]

I have a bit of a confusing timing issue. I have a source synchronous DDR LVDS output interface in which the data and clock are centre aligned. 

This all passes timing and I am happy with all the timing constraints. The clock is running at 360MHz. As an experiment I added a clock gate on to the   LVDS output clock. I found that the addition of this function added 1.5ns to my clock path. This killed my timing meaning my setup time   was 1.3ns positive slack but my hold time slack was -1.6ns.  I left my create generated clock constraint for generating the latch clock as 90deg to the launch clock. To hopefully bring the   clock back to passing hold time, I thought I could adjust the PLL back to 0 deg and recover some of the delay. However, when   I do this, the setup and hold time remain the same. I know the PLL is changing but I am confused as to why the timing isn't   improving. Should I have adjusted the generated clock constraint as well to reflect the new pll phase  Thanks in advance

[Altera_Forum]

If you use the "create_ generated_clock" command in your SDC, yes; You should modify your constraints in order to reflect phase shift. 

If you have used the "derive_pll_clocks" in the SDC file, no; It is automatically translated into appropriate commands.

[Altera_Forum]

Thanks for the confirmation msj