Timequest and Async Paths

[Altera_Forum]

Hello: 

I have a simple CPLD design that has an async input pin that goes to a latch. From the latch it goes to an async output pin. I would like to constrain the input path from the pin to the latch to be 30ns as well as constrain the latch to the output pin to be 30ns. How can I do this without having timequest include the clock delay?  Additioanlly, the path from the latch to the async output pin is routed through several stages of LUTs. These LUTs have sync control for gating the value from being propagated. I would like to constrain the path from the sync control though the LUT to the async output pin to be 30ns. How can I do this without having timequest include the clock delay?  The only method I have found that is close is set_min_delay/set_max_delay. However this is still not ideal as I don't need it to analyze any clocks, I just need the routing delay verified.  Thanks in advance for your help!

[Altera_Forum]

Not sure if this will help 

You can use set_max/min_delay without any clocks. I've used it to constrain purely combinational paths, ie: set_max_delay from [get_ports A] -to [get_ports B] 10  Another possibility it to add clocked external delays (set_input/ouput_delay) based on a virtual clock. create_clock -name virtual_clk_for_async -period 100 set_input_delay -clock virtual_clk_for_async -max 45 [get_ports A] set_output_delay -virtual_clk_for_async -max 45 [get_ports B] # Set clock groups to exclude paths from the real clock and and aync clock domains set_clock_groups -asynchrnous {clk} {virtual_clk_for_async}  If I didn't get anything wrong, this will have the same effect as the line above.

[Altera_Forum]

I have tried the virtual clocks and I can keep trying. To help I made a simple diagram representing what I am doing. I am setting up 2-to-1 LCELLs to do async logic glitchless and then I have a SR-LATCH implemented in a LUT to control my logic. It must be async and I verified with the floorplanner. 

I want to constrain the path from the flop's clock to out, through its routing delay to the LCELL, through the LCELL and ultimately to the SR-LATCH to be one clock period- 33ns. I then desire the Async in through the input delay through the LCELL, and then through the routing to the SR-LATCH to be 33ns as well. Finally the LCELL output routed to the pin (maybe through more LCELLS) to also be 33ns. How do I do this with virtual clocks? I will try some of your suggestions as well. Let me know of any suggestions. Thanks!

[Altera_Forum]

I'm not really getting your goal... 

 Is the source of AsyncIn really asynchronous to the clock? Is the destination of AsyncOut really asynchronous to the clock? And if so, what is the purpose of the clocked logic?  BTW, trying to constrain a delay to be excatly X ns is not possible due to PVT variations. You can only constrain to a range.

[Altera_Forum]

I included an updated diagram, responses: 

 1) Is the source of AsyncIn really asynchronous to the clock? -Yes 2) Is the destination of AsyncOut really asynchronous to the clock? -Yes 3) And if so, what is the purpose of the clocked logic? -The diagram is a VERY simplified representation (updated below), the clocked logic is used to implement async 2-to-1 muxes in series, gate off set while the latch is being reset, etc. I want to be sure if I am configuring muxes or resetting latches that I do not say my configuration is complete until some amount of time afterwards so my async logic does not glitch. Therefore I use a 2-to-1 mux on the latch set lines and the async output to enforce this and I need to constrain the prop delay from the flop to make sure the assumption for gating off it met. 4) BTW, trying to constrain a delay to be exactly X ns is not possible due to PVT variations. You can only constrain to a range. - Correct, I am looking for a 0-33ns range