Timequest clock reference

[Altera_Forum]

Hi 

 I am looking for a way to move timequest clock reference point from the pin to the internal global clock net?  Being able to do that would make it must easier to make and understand timeconstrains, and second it will take the absolute delay from pin to global net out off the equation and make timing closure easier.

[Altera_Forum]

When creating constraints, you need only to describe your needs and then let TimeQuest handle the rest -- TimeQuest knows all about the internal charateristics of the FPGA.  

TimeQuest will handle the delay from the pin to the clock network, and the skew along the clock network and whatever more has to be taken account inside the FPGA.

[Altera_Forum]

Hi 

 You right in some general aspect. Timequest will handle the delays and the skews. But the problem is that it should not because the delay from the pin to the global net is NOT relevant in my designs. This is because there is NO HW relelated to this external clock source. The pin to global net delay varies a lot from fast to slow corner somethink like 0.8nS to 2.5nS! Timequest takes this variation into the analyse I can see that. But as I use source synchronous interface this variation should not be included in the analyse. Timequest can not know this onless I tell it. The logical way is to use the internal global net as the reference instead of the pin but there can be some other way?  There is one common reference clock: the internal global net, lets call it CLK_80M while we call the PIN feeding the global net CLK_80M_PIN. Normal behave in Timequest is to relate the timing to the pin. This makes sense if you have external HW related to the clock source driving the pin. But none of our interfaces does this as this is a non optimal way of doing fast interfaces. The common for all my interfaces are that they are source synchronous using a PLL in the FPGA or in the external device.  Lets take one simple interface. No data DDR to start with. The FPGA is making the clock for the source synchronnous interface with a PLL and an I/O register. CLK_80M_PIN feeds CLK_80M global net. CLK_80M feeds the PLL input making an output clock pin SR_CLK which has the same frequency as CLK_80M and is phase locked. (the PLL output clock use a regional clock net and I/O register in a special way to avoid variable routning delay and optimize timing but it does not matter for the timing coinstrains and analyse) CLK_80M global clocks data out and CLK_80M global clocks data in. So all timing in timequest is should be from CLK_80M global to SR_CLK or from SR_CLK to CLK_80M global. My problem is that timequest do not analyse this it analyse from CLK_80M_Pin to SR_CLK and vice versa. The delay from CLK_80M_PIN  to CLK_80M global net is included in the analyze which is not ideel and makes it much more complicated for me to understand and verify. So how do I make I make timequest do the timing analyse between the global net and my I/O clock instead of analyzing between the global net pin source which is irrrelevant. (This is what I call moving the reference point, I do not know what else to call it). Another way to ask is how do I generate a timequest clock for the internal global clock net?

[Altera_Forum]

Ah, I think I see your problem. 

I suggest you read the document that Rysc wrote: http://www.alteraforum.com/forum/showthread.php?t=4806  It should help you.

[Altera_Forum]

Thanks for hint. 

I finally got a breakthrough 1 hour ago: It is actually very simple, properly so simple you did not realize what I was trying to do. Instead of using  create_clock -name {CLK_80M} -period 12.500 -waveform { 0.000 6.250 } [get_ports {CLK_80M}] I should forget about the pin and make a base clock directly on the post synthesized global net as pre-synthesized signal name is interpreted as the pin) create_clock -name {CLK_80M_INTERNAL} -period 12.500 -waveform { 0.000 6.250 } [get_pins {CLK_80M~clkctrl|outclk}]  nb For other beginners I can add that in Timequest a pin is not a pin. A pin is called a port and a pins means an input or output of an internal FPGA primitive.   Case closed