Timequest makes timings but not the real stratix IV hardware

[Altera_Forum]

I am having problems making actual timings on the real hardware. I'm actually trying to upgrade from a stratix III to a stratix IV. The design works on a stratix III. 

 After I've set up a basic constraint file (.sdc), I see Timequest properly identifying my main clocks and telling me that I'm making timings with no problem. Yet my stratix IV hardware still isn't making timings. I can use the signaltap to see how some of my waveforms at some particular point begin to contain glitches like distortions. These glitches only appear as I am integrating more and more things into the FPGA. So the problems begin only as the chip uses more resources and consumes more current. Also, I can usually improve the distorted signal as I cool the chip with an anti-static freezer.  I don't know what to do because according to timequest, my Fmax is well above what I need, e.g., 149MHz when I need only 120Mhz, and 312Mhz when I need only 240 Mhz.  I should also mention that this is a multi-rate design. There is a main clock but actual data rates are controlled by toggling the clock enable of the registers. Now, I haven't declared any multi-cycle paths in the constrained file, however, I would have expected in this case that this would be an issue only if I had not made timings.  Any suggestions?

[Altera_Forum]

--- Quote Start ---  I am having problems making actual timings on the real hardware. I'm actually trying to upgrade from a stratix III to a stratix IV. The design works on a stratix III.  After I've set up a basic constraint file (.sdc), I see Timequest properly identifying my main clocks and telling me that I'm making timings with no problem. Yet my stratix IV hardware still isn't making timings. I can use the signaltap to see how some of my waveforms at some particular point begin to contain glitches like distortions. These glitches only appear as I am integrating more and more things into the FPGA. So the problems begin only as the chip uses more resources and consumes more current. Also, I can usually improve the distorted signal as I cool the chip with an anti-static freezer.  I don't know what to do because according to timequest, my Fmax is well above what I need, e.g., 149MHz when I need only 120Mhz, and 312Mhz when I need only 240 Mhz.  I should also mention that this is a multi-rate design. There is a main clock but actual data rates are controlled by toggling the clock enable of the registers. Now, I haven't declared any multi-cycle paths in the constrained file, however, I would have expected in this case that this would be an issue only if I had not made timings.  Any suggestions?  --- Quote End ---    Hi,  are all clocks, I/O paths constraint ? Timequest can analyze your design regarding un-constraint paths and clock transfers. Start Timequest , open the Diagnostic folder in the Tasks window. Run "Report Clock Transfers" and "Report Unconstrained Paths".  Kind regards  GPK

[Altera_Forum]

Thanks for the reply. No, not all paths are constrained. But there are just too many according to the report, but most of them should not be relevant to the problem at hand. The clocks that are involved in the circuitry are constrained and are making timings according to the tool. The only thing I'm not sure about is how the Quartus II handles the enable pins of the registers that are toggled for controlling the data rate.

[Altera_Forum]

--- Quote Start ---  Thanks for the reply. No, not all paths are constrained. But there are just too many according to the report, but most of them should not be relevant to the problem at hand. The clocks that are involved in the circuitry are constrained and are making timings according to the tool. The only thing I'm not sure about is how the Quartus II handles the enable pins of the registers that are toggled for controlling the data rate.  --- Quote End ---    Hi,  do you have different clock domains ? Do you have a look to the clock transfer results ? Are all clock domain crossings properly designed ?  Why are so many paths not constraint ? Are that I/O or internal paths ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Why are so many paths not constraint ? Are that I/O or internal paths ?  --- Quote End ---    Most of them are I/Os but there are also some internal clocks. This design was designed for the stratix III with the classic analyzer. I've just recently upgraded to the stratix IV. With the classic analyzer, I've managed to get by without much worrying about constraints. The design worked. Now, I can't get the design to work despite the fact that I have a faster speed grade device.    --- Quote Start ---  Do you have a look to the clock transfer results ? Are all clock domain crossings properly designed ?  --- Quote End ---    The report says that there is one "false path". But these Clocks are not in any way involved in that section that I am observing the timing failures.

[Altera_Forum]

--- Quote Start ---  Most of them are I/Os but there are also some internal clocks. This design was designed for the stratix III with the classic analyzer. I've just recently upgraded to the stratix IV. With the classic analyzer, I've managed to get by without much worrying about constraints. The design worked. Now, I can't get the design to work despite the fact that I have a faster speed grade device.    The report says that there is one "false path". But these Clocks are not in any way involved in that section that I am observing the timing failures.  --- Quote End ---    Hi,  only to be sure that I don't misunderstand something:  You have a design on StratixIII , using the Classic Timing Analyzer which runs. Then you changed to StratixIV ( now you have to use TimeQuest, I believe) and now the design isn't running anymore, right ?  Any hold time violations ?  Kind regards  GPK

[Altera_Forum]

Yes, Not running as in not making timings, although the analyzer says I am. I have some violations with one particular clock that is not involved in the relevant circuits at all. I can disable it and the violations will go away. Then nothing is in red any more except for the report of unconstrained paths.

[Altera_Forum]

--- Quote Start ---  Yes, Not running as in not making timings, although the analyzer says I am. I have some violations with one particular clock that is not involved in the relevant circuits at all. I can disable it and the violations will go away. Then nothing is in red any more except for the report of unconstrained paths.  --- Quote End ---    Hi,  you observed the problem with signaltap. It is also possible that you have a problem with  capturing the signals. Could you verify that your design shows a "real" misbehaviour ?  Kind regards  GPK

[Altera_Forum]

I actually observe the problem outside the chip. I have a DAC and I observe the problem on the waveform itself. Only then did I go and use the signal tap to try to isolate the problem. The distortions I get in the captured signals with signal tap are pretty much aligned with what I observe outside the chip.

[Altera_Forum]

--- Quote Start ---  I actually observe the problem outside the chip. I have a DAC and I observe the problem on the waveform itself. Only then did I go and use the signal tap to try to isolate the problem. The distortions I get in the captured signals with signal tap are pretty much aligned with what I observe outside the chip.  --- Quote End ---    Hi,  which timing checks did you run with Timequest ?   Kind regards  GPK

[Altera_Forum]

What do you mean? There are all of the summary reports provided in the compilation report. According to that report, I am making timings.

[Altera_Forum]

--- Quote Start ---  What do you mean? There are all of the summary reports provided in the compilation report. According to that report, I am making timings.  --- Quote End ---    Hi,  as far as I know you get only the worst-case timing as default. Maybe your design is now to fast. First you can check whether the "Optimize multi-corner timing" is switched on. You find it under Settings -> Fitter Settings. If it is enabled Quartus also considers  the fast timing for the implementation. Did you specify a <>.sdc file ? If yes, can you post it ?  Kind regards  GPK

[Altera_Forum]

I get 2 slow reports and one fast. I pass all 3. the multi-corner timing is switched on.

[Altera_Forum]

I have identified the precise place where timings are not being met: 

  I have a barrel shifter that is purely combinatory between two registers. It's quite big with about 70 plus bits in size. Both registers receive the same clock. The clock has made timings according to the analyzer. The question is: Why is the analyzer not properly calculating the delays of this barrel shifter?

[Altera_Forum]

--- Quote Start ---  I have identified the precise place where timings are not being met:   I have a barrel shifter that is purely combinatory between two registers. It's quite big with about 70 plus bits in size. Both registers receive the same clock. The clock has made timings according to the analyzer. The question is: Why is the analyzer not properly calculating the delays of this barrel shifter?  --- Quote End ---    Hi,  dit they use the same clock enable signals ? Can you try to check the timing of the paths directly in Timequest ?  Kind regards  GPK