Timequest output to extrernal device SDC question

[Altera_Forum]

I was attempting to create a SDC file to constrain my outputs but I think I do not understand the case when the FPGA drives an external device with its own clock. For the FPGA inputs I feel like I understand why and how to create use a virtual clock and set the input delay. When I attempt to follow examples for the outputs I get confused or rather I follow the examples and I dont feel like I understand whats going on. 

 So my FPGA design drives the output pin from a registers using an internal clock, and it also outputs the internal clock. I read the TimeQuest User Guide for example, but they show dac being driven from a external system clock source and adjusting set_output_delay and set_clock_latency.  So in my case FPGA sources both data and clock. So I feel like I am not supposed to create a virtual clock. I attached a very simple schematic with a data and clock output with equal length board delays.   I appreciate any help.

[Altera_Forum]

First, you need to create a derived clock on the FPGA's clock output pin.  

 Then, you set the output delay constraints relative to that clock. Something like:  create_clock -name clkin1 -period 10 create_generated_clock -source clkin1 -name clkout1 set_input_delay -clock clkout1 -min $minDelay set_input_delay -clock clkout1 -max $maxDelay   with minDelay = -tHold - margin maxDelay = tSetup + margin the margin is to account for different PCB delays between the clock and the data signals

[Altera_Forum]

Note that your clock and data will be going out very close to each other. With default analysis, this is close to a hold violation. Quite often users will invert the clock going off chip. If you do this, be sure to add -invert to the generated clock. With rbugalho's example, the default setup relationship is 10ns and hold is 0ns. If you invert the clock, then the setup relationship becomes 5ns and hold becomes -5ns.

[Altera_Forum]

Hi rbugalho, 

  I assume you meant set_output_delay instead of set_input_delay. Thanks for the example.

[Altera_Forum]

I have another question. So I added the set_output_delays and create_generated_clock statements, but Quartus/Timequest reports unconstrained paths for setup and hold from clkin1 to clkout1.  

 Back to the simple schematic attachment, I am passing the clock input to the FPGA to a output pin ungated. So I do not understand these errors:  *Unconstrained input port paths: From:clkin1, To:clkout1 *Unconstrained output port paths: From:clkin1, To:Clkout1  I tried all the various commands like set_max_delay between two clocks but the error persists.

[Altera_Forum]

Hi, 

yes, I meant set_output_delay.  TimeQuest is complaining because you haven't put restrictions on the delay between clkin1 and clkout1. You can either a) set_max_delay AND set_min_delay b) set_false_path, which is what I'd do c) ignore TimeQuest (which is the same as option b)

[Altera_Forum]

TimeQuest reports outputs unconstrained if they dont' have a set_output_delay or set_false_path on them. I've tried to get this changed, since having a clock constraint on it is just as good. (Otherwise you could argue that clock inputs are "unconstrained"). I would recommend doing c) and ignore it. If you put a set_max/min_delay, you're constraining it in a way you don't want to. (What you want is your output data port constrained in relation to this clock, which you've successfully done). Putting a set_false_path on it might work, but it might cut the clock analysis. I'm not sure.

[Altera_Forum]

Option b) works, but it does need a big red warning. 

 If you use set_false_path -from -to  then, it just sets cut the path between the pins from analysis and just stops TimeQuest from complaining about unconstrained paths.  But if you use set_false_path -from -to  then it cuts all paths between those two clocks from analysis. Totally not what you want.