​Hi
I have an internal data clock derived from a pll in my device. I am clocking the output data of my system with a phase shifted version of my internal data clock from the same pll.
Why does Timequest show the launch clock (internal clock) and latch (phase shifted clock) edges in phase with each other regardless of the phase difference I set into the pll?
I am having difficulty specifying my set_output_delay constraints referenced to the delayed clock as it seems timequest is ignoring the phase shift from the internal clock.
Thanks
Dave
